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7480 Scheda tecnica(PDF) 323 Page - Renesas Technology Corp

Il numero della parte 7480
Spiegazioni elettronici  8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES
PDF  337 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7480 Scheda tecnica(HTML) 323 Page - Renesas Technology Corp

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Addressing mode
Symbol
Function
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
OP n# OP n# OP n# OP n# OP n#
OP n
#
3-58
3.6 Machine Instructions
7480 Group and 7481 Group User's Manual
APPENDICES
Jumps to the specified address.
After storing contents of program counter in
stack, and jumps to the specified address.
Load accumulator with contents of memory.
Load memory indicated by index register X
with contents of memory specified by the ad-
dressing mode.
Load memory with immediate value.
Load index register X with contents of
memory.
Load index register Y with contents of
memory.
Shift the contents of accumulator or memory
to the right by one bit.
The low order bit of accumulator or memory is
stored in carry, 7th bit is cleared.
Multiplies the accumulator with the contents of
memory specified by the zero page X address-
ing mode and stores the high byte of the result
on the stack and the low byte in the accumula-
tor.
No operation.
“Logical OR’s” the contents of memory and ac-
cumulator. The result is stored in the
accumulator.
“Logical OR’s” the contents of memory indi-
cated by index register X and contents of
memory specified by the addressing mode.
The result is stored in the memory specified by
index register X.
JMP
JSR
LDA
(Note 2)
LDM
LDX
LDY
LSR
MUL
NOP
ORA
(Note 1)
If addressing mode is ABS
PCL
← ADL
PCH
← ADH
If addressing mode is IND
PCL
← M (ADH, ADL)
PCH
← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL
← M(00, ADL)
PCH
← M(00, ADL + 1)
M(S)
← PCH
S
← S – 1
M(S)
← PCL
S
← S – 1
After executing the above,
if addressing mode is ABS,
PCL
← ADL
PCH
← ADH
if addressing mode is SP,
PCL
← ADL
PCH
← FF
If addressing mode is ZP, IND,
PCL
← M(00, ADL)
PCH
← M(00, ADL + 1)
When T = 0
A
← M
When T = 1
M(X)
← M
M
← nn
X
← M
Y
← M
M(S) · A ← A ! M(zz + X)
S
← S – 1
PC ← PC + 1
When T = 0
A
← A V M
When T = 1
M(X)
← M(X) V M
A9
A2
A0
09
4A 2
1
A5
3C
A6
A4
46
05
3
4
3
3
5
3
2
3
2
2
2
2
EA 2
1
2
2
2
2
2
2
2
2
7
0
0
→C



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