Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. 00A

6/4/2013

Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without

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version of this device specification before relying on any published information and before placing orders for products.

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IS43/46DR81280C

IS43/46DR16640C

ADVANCED INFORMATION

MAY 2013

128Mx8, 64Mx16 DDR2 DRAM

FEATURES

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Double data rate interface: two data transfers

per clock cycle

• Differential data strobe (DQS, DQS)

• 4-bit prefetch architecture

• On chip DLL to align DQ and DQS transitions

with CK

• 8 internal banks for concurrent operation

• Programmable CAS latency (CL) 3, 4, 5, 6 and 7

supported

• Posted CAS and programmable additive latency

(AL) 0, 1, 2, 3, 4, 5 and 6 supported

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength, full and

reduced strength options

• On-die termination (ODT)

OPTIONS

• Configuration(s):

128Mx8 (16Mx8x8 banks): IS43/46DR81280C

64Mx16 (8Mx16x8 banks): IS43/46DR16640C

• Package:

x8: 60-ball BGA (8mm x 10.5mm)

x16: 84-ball WBGA (8mm x 12.5mm)

• Timing – Cycle time

2.5ns @CL=5 DDR2-800D

2.5ns @CL=6 DDR2-800E

3.0ns @CL=5 DDR2-667D

3.75ns @CL=4 DDR2-533C

5ns @CL=3 DDR2-400B

• Temperature Range:

Commercial (0°C ≤ Tc ≤ 85°C)

DESCRIPTION

ISSI's 1Gb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double-data rate architecture is essentially a 4n-prefetch

architecture, with an interface designed to transfer two

data words per clock cycle at the I/O balls.

Parameter

128M x 8

64M x 16

Configuration

16M x 8 x 8

banks

8M x 16 x 8

banks

Refresh Count

8K/64ms

8K/64ms

Row Addressing

16K (A0-A13) 8K (A0-A12)

Column

Addressing

1K (A0-A9)

1K (A0-A9)

Bank Addressing BA0 - BA2

BA0 - BA2

Precharge

Addressing

A10

A10

ADDRESS TABLE

Speed Grade

-25D

-3D

tRCD

12.5

15

tRP

12.5

15

tRC

55

55

tRAS

40

40

tCK @CL=3

5

5

tCK @CL=4

3.75

3.75

tCK @CL=5

2.5

3

tCK @CL=6

2.5

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KEY TIMING PARAMETERS