IS46DR16640C datasheet(28/49 Pages) ISSI

28 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

20. Input waveform timing tDS with differential data strobe enabled is referenced from the input signal crossing at

the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the

VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS

signals must be monotonic between Vil(dc)max and Vih(dc)min.

21. Input waveform timing tDH with differential data strobe enabled is referenced from the differential data strobe

crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from the differential data strobe

crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the device under test. DQS,

DQS signals must be monotonic between Vil(dc)max and Vih(dc)min.

22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and

VIL(ac) for a falling signal applied to the device under test.

23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and

VIH(dc) for a falling signal applied to the device under test.

24. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.

25. Input waveform timing with single-ended data strobe enabled, is referenced from the input signal crossing at the

VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and

from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its

transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max

and Vih(dc)min.

26. Input waveform timing with single-ended data strobe enabled, is referenced from the input signal crossing at the

VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and

from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its

transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max

and Vih(dc)min.

27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain

at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition,

CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH.

28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid

READ can be executed.

29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1,

etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount

of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that

latches the command/address. That is, these parameters should be met whether clock jitter is present or not.

30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock

signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc),

etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is

present or not.

31. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its

respective data strobe signal ((L/U/R)DQS/ DQS) crossing.

32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM

/ tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.

For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter

specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP

/ tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active

command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter.

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