IS46DR16640C datasheet(36/49 Pages) ISSI

36 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

Burst mode operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory

locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst

length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address

ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst

type, either sequential or interleaved, is programmable and defined by MR[A3], which is similar to the DDR SDRAM

operation. Seamless burst read or write operations are supported. Unlike DDR devices, interruption of a burst read or

write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or

write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst

Stop command is not supported on DDR2 SDRAM devices.

Burst Length and Sequence

Burst Length Starting Address (A1, A0) Sequential Addressing (decimal)

Interleave Addressing (decimal)

0 0

0, 1, 2, 3

0 1

1, 2, 3, 0

1, 0, 3, 2

1 0

2, 3, 0, 1

1 1

3, 0, 1, 2

3, 2, 1, 0

Burst Length Starting Address (A2, A1, A0) Sequential Addressing (decimal)

Interleave Addressing (decimal)

0 0 0

0, 1, 2, 3, 4, 5, 6, 7

0 0 1

1, 2, 3, 0, 5, 6, 7, 4

1, 0, 3, 2, 5, 4, 7, 6

0 1 0

2, 3, 0, 1, 6, 7, 4, 5

0 1 1

3, 0, 1, 2, 7, 4, 5, 6

3, 2, 1, 0, 7, 6, 5, 4

1 0 0

4, 5, 6, 7, 0, 1, 2, 3

1 0 1

5, 6, 7, 4, 1, 2, 3, 0

5, 4, 7, 6, 1, 0, 3, 2

1 1 0

6, 7, 4, 5, 2, 3, 0, 1

1 1 1

7, 4, 5, 6, 3, 0, 1, 2

7, 6, 5, 4, 3, 2, 1, 0

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