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IS46DR16640C Scheda tecnica(PDF) 17 Page - Integrated Silicon Solution, Inc |
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IS46DR16640C Scheda tecnica(HTML) 17 Page - Integrated Silicon Solution, Inc |
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17 / 49 page  Integrated Silicon Solution, Inc. — www.issi.com 17 Rev. 00A 6/4/2013 IS43/46DR81280C, IS43/46DR16640C Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Symbol DDR2-400 DDR2-553 Units Notes Min. Max. Min. Max Clock cycle time, CL=x tCK 5 8 3.75 8 ns 15 CK HIGH pulse width tCH 0.45 0.55 0.45 0.55 tCK CK LOW pulse width tCL 0.45 0.55 0.45 0.55 tCK DQS latching rising transitions to associated clock edges tDQSS - 0.25 0.25 - 0.25 0.25 tCK DQS falling edge to CK setup time tDSS 0.2 – 0.2 – tCK DQS falling edge hold time from CK tDSH 0.2 – 0.2 – tCK DQS input HIGH pulse width tDQSH 0.35 – 0.35 – tCK DQS input LOW pulse width tDQSL 0.35 – 0.35 – tCK Write preamble tWPRE 0.35 – 0.35 – tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 10 Address and control input setup time tIS(base) 350 – 250 – ps 5, 7, 9, 22 Address and control input hold time tIH(base) 475 – 375 – ps 5, 7, 9, 23 Control & Address input pulse width for each input tIPW 0.6 – 0.6 – tCK DQ and DM input setup time (differential strobe) tDS(base) 150 – 100 – ps 6, 7, 8, 20, 28 DQ and DM input hold time (differential strobe) tDH(base) 275 – 225 – ps 6, 7, 8, 21, 28 DQ and DM input setup time (single-ended strobe) tDS1(base) 25 – - 25 – ps 6, 7, 8, 25 DQ and DM input hold time (single-ended strobe) tDH1(base) 25 – - 25 – ps 6, 7, 8, 26 DQ and DM input pulse width for each input tDIPW 0.35 – 0.35 – tCK DQ output access time from CK/CK tAC - 600 + 600 - 500 + 500 ps DQS output access time from CK/ CK tDQSCK - 500 + 500 - 450 + 450 ps Data-out high-impedance time from CK/ CK tHZ – tAC max – tAC max ps 18 DQS(DQS) low-impedance time from CK/ CK tLZ(DQS) tAC min tAC max tAC min tAC max ps 18 DQ low-impedance time from CK/ CK tLZ(DQ) 2 x tAC min tAC max 2 x tAC min tAC max ps 18 DQS-DQ skew for DQS and associated DQ signals tDQSQ – 350 – 300 ps 13 CK half pulse width tHP min (tCL, tCH) – min (tCL, tCH) – ps 11,12 DQ hold skew factor tQHS – 450 – 400 ps 12 DQ/DQS output hold time from DQS tQH tHP - tQHS – tHP - tQHS – ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 19 Read postamble tRPST 0.4 0.6 0.4 0.6 tCK 19 |
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