IS46DR16640C datasheet(32/49 Pages) ISSI

32 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

FUNCTIONAL DESCRIPTION

Power-up and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation. For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/

Extended Mode Register Set (MRS/EMRS) commands. Users must initialize all four Mode Registers. The registers

may be initialized in any order.

Power-up and Initialization Sequence

The following sequence is required for Power-up and Initialization.

a) Either one of the following sequence is required for Power-up.

a1) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT*1 at a LOW state (all other

inputs may be undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps

from 300 mV to VDD min; and during the VDD voltage ramp, |VDD-VDDQ| ≤ 0.3 volts. Once the ramping of the

supply voltages is complete (when VDDQ crosses VDDQ min), the supply voltage specifications provided in

"Recommended DC operating conditions" (SSTL_1.8), prevail.

- VDD, VDDL and VDDQ are driven from a single power converter output, AND

- VTT is limited to 0.95V max, AND

- VREF tracks VDDQ/2, VREF must be within +/- 300mV with respect to VDDQ/2 during supply ramp time.

- VDDQ ≥ VREF must be met at all times.

a2) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT*1 at a LOW state, all other inputs

may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid

DRAM latch-up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is

applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ

crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specifications provided

in "Recommended DC operating conditions" (SSTL_1.8), prevail.

- Apply VDD/VDDL before or at the same time as VDDQ.

- VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min

- Apply VDDQ before or at the same time as VTT.

- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ

must be no greater than 500ms.

(Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.)

- VREF must track VDDQ/2, VREF must be within +/- 300mv with respect to VDDQ/2 during supply ramp time.

- VDDQ ≥ VREF must be met at all times.

- Apply VTT.

- The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT must

be no greater than 500ms.

b) Start clock and maintain stable condition.

c) For the minimum of 200

ms after stable power (VDD, VDDL, VDDQ, VREF and VTT are between their minimum and

maximum values as stated in "Recommended DC operating conditions" (SSTL_1.8)) and stable clock (CK, CK), then

apply NOP or Deselect & take CKE HIGH.

d) Wait minimum of 400ns then issue precharge all command. NOP or Deselect applied during 400 ns period.

e) Issue an EMRS command to EMR(2).

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