IS46DR16640C datasheet(39/49 Pages) ISSI

39 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

Extended Mode Register 2 (EMR2)

The Extended Mode Register 2 controls refresh related features. The default value of the EMR(2) is not defined,

therefore the mode register must be programmed during initialization for proper operation. The EMR(2) is written

by asserting LOW on CS, RAS, CAS, WE, HIGH on BA1 and LOW on BA0 and BA2, while controlling the states

of address pins A0 - A13. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior

to writing into the EMR(2). The mode register set command cycle time (tMRD) must be satisfied to complete the

write operation to the EMR(2). Mode register contents can be changed using the same command and clock cycle

requirements during normal operation as long as all banks are in the precharge state.

EMR(2)

Address

Field

Mode

BA1

BA2

BA0

A12

A13*1,3

A11*1

A10*1

A9*1

High Temperature Self-Refresh Rate Enable

Disable

Enable*2

A8*1

SRF

A6*1

A5*1

A4*1

A3*1

A2*1

A1*1

A0*1

Notes:

1. A0-A6, A8-A13 are reserved for future use and must be set to 0 when programming the EMR(2).

2. Only Industrial and Automotive grade devices support the high temperature Self-Refresh Mode. The controller can set the EMR (2) [A7] bit to

enable this self-refresh rate if Tc > 85oC while in self-refresh operation. Toper may not be violated.

3. A13 is only applicable for x8.

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