Integrated Silicon Solution, Inc. — www.issi.com

41

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

TRUTH TABLES

Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation,

the DRAM must be powered down and then restarted through the speechified initialization sequence before normal

operation can continue.

Command Truth Table

Function

CKE

CS

RAS

CAS

WE

BA2 -

BA0

A13-

A11

A10

A9-A0

Notes

Previous

Cycle

Current

Cycle

(Extended) Mode

Register Set (Load

Mode)

H

H

L

L

L

L

BA

OP Code

1, 2

Refresh (REF)

H

H

L

L

L

H

X

X

X

X

1

Self Refresh Entry

H

L

L

L

L

H

X

X

X

X

1, 8

Self Refresh Exit

L

H

H

X

X

X

X

X

X

X

1, 7, 8

L

H

H

H

Single Bank

Precharge

H

H

L

L

H

L

BA

X

L

X

1, 2

Precharge all Banks

H

H

L

L

H

L

X

X

H

X

1

Bank Activate

H

H

L

L

H

H

BA

Row Address

1,2,10

Write

H

H

L

H

L

L

BA

X

L

Column

1, 2, 3

Write with Auto

Precharge

H

H

L

H

L

L

BA

X

H

Column

1, 2, 3

Read

H

H

L

H

L

H

BA

X

L

Column

1, 2, 3

Read with Auto-

Precharge

H

H

L

H

L

H

BA

X

H

Column

1, 2, 3

No Operation

H

X

L

H

H

H

X

X

X

X

1

Device Deselect

H

X

H

X

X

X

X

X

X

X

1

Power Down Entry

H

L

H

X

X

X

X

X

X

X

1, 4

L

H

H

H

Power Down Exit

L

H

H

X

X

X

X

X

X

X

1, 4

L

H

H

H

Notes:

1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.

2. Bank addresses BA0, BA1 and BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.

3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a

Write" for details.

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements

5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 3.4.4.

6. “X” means “H or L (but a defined logic level)”

7. Self refresh exit is asynchronous.

8. VREF must be maintained during Self Refresh operation.

9. BAx and Axx refers to the MSBs of bank addresses and addresses, respectively.

10. For x16 option, A13 is "Don't Care" (X) for Activate.