IS46DR16640C datasheet(44/49 Pages) ISSI

44 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.

The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command

is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank

is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing

parameters. After a bank has been precharged, it is in the idle state and must be activated prior to any READ or

WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that

bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period

will be determined by the last PRECHARGE command issued to the bank.

REFRESH

REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS-before-RAS (CBR)

REFRESH. All banks must be in the idle mode prior to issuing a REFRESH command. This command is

nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh

controller. This makes the address bits a “Don’t Care” during a REFRESH command.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power

supply inputs (including VREF) must be maintained at valid levels upon entry/exit and during SELF REFRESH

operation.

The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically

disabled upon entering self refresh and is automatically enabled upon exiting self refresh.

ODT (On-Die Termination)

The On-Die Termination feature allows the DDR2 SDRAM to easily implement a termination resistance (Rtt) for each

DQ, DQS, DQS, RDQS, and RDQS signal. The ODT feature can be configured with the Extended Mode Register Set

(EMRS) command, and turned on or off using the ODT input signal. Before and after the EMRS is issued, the ODT

input must be received with respect to the timings of tAOFD, tMOD(max), tAOND; and the CKE input must be held

HIGH throughout the duration of tMOD(max).

The DDR2 SDRAM supports the ODT on and off functionality in Active, Standby, and Power Down modes, but not in

Self Refresh mode. ODT timing diagrams follow for Active/Standby mode and Power Down mode.

EMRS to ODT Update Delay

EMRS

CMD

NOP

ODT

tMOD,max

tMOD,min

Old setting

ODT ReadyUpdated

Rtt

tAOFD

tIS

tAOND

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