IS46DR16640C datasheet(19/49 Pages) ISSI

19 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

Parameter

Symbol

DDR2-667

DDR2-800

Units

Notes

Min.

Max.

Min.

Max

Average clock period

tCK(avg)

2.5

35,36

Average clock HIGH pulse width

tCH(avg)

0.45

0.55

0.45

0.55

tCK(avg)

35,36

Average clock LOW pulse width

tCL(avg)

0.45

0.55

0.45

0.55

tCK(avg)

35,36

DQS latching rising transitions to associated

clock edges

tDQSS

- 0.25

0.25

- 0.25

0.25

tCK(avg)

DQS falling edge to CK setup time

tDSS

0.2

–

0.2

–

tCK(avg)

DQS falling edge hold time from CK

tDSH

0.2

–

0.2

–

tCK(avg)

DQS input HIGH pulse width

tDQSH

0.35

–

0.35

–

tCK(avg)

DQS input LOW pulse width

tDQSL

0.35

–

0.35

–

tCK(avg)

Write preamble

tWPRE

0.35

–

0.35

–

tCK(avg)

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK(avg)

Address and control input setup time

tIS(base)

200

–

175

–

5, 7, 9, 22,

Address and control input hold time

tIH(base)

275

–

250

–

5, 7, 9, 23,

Control & Address input pulse width for each

input

tIPW

0.6

–

0.6

–

tCK(avg)

DQ and DM input setup time

tDS(base)

–

6, 7, 8, 20,

28, 31

DQ and DM input hold time

tDH(base)

175

–

125

–

6, 7, 8, 21,

28, 31

DQ and DM input pulse width for each input

tDIPW

0.35

–

0.35

–

tCK(avg)

DQ output access time from CK/CK

tAC

- 450

450

- 400

400

DQS output access time from CK/CK

tDQSCK

- 400

400

- 350

350

Data-out high-impedance time from CK/CK

tHZ

–

tAC,max

–

tAC,

max

18,40

DQS/DQS low-impedance time from CK/CK

tLZ(DQS)

tAC,min

tAC,max

tAC,min

tAC,

max

18,40

DQ low-impedance time from CK/CK

tLZ(DQ)

2 x tAC,min tAC,max 2 x tAC,min

tAC,

max

18,40

DQS-DQ skew for DQS and associated DQ

signals

tDQSQ

–

240

–

200

CK half pulse width

tHP

Min(

tCH(abs),

tCL(abs) )

–

Min(

tCH(abs),

tCL(abs) )

–

DQ hold skew factor

tQHS

–

340

–

300

DQ/DQS output hold time from DQS

tQH

tHP - tQHS

–

tHP - tQHS

–

Read preamble

tRPRE

0.9

1.1

0.9

1.1

tCK(avg)

19,41

Read postamble

tRPST

0.4

0.6

0.4

0.6

tCK(avg)

19,42

Timing Parameters by Speed Grade (DDR2-667 and DDR2-800)

(For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.)

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