IS46DR16640C datasheet(3/49 Pages) ISSI

3 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

Symbol

Type

Function

CK, CK

Input

Clock: CK and CK are differential clock inputs. All address and control input signals

are sampled on the crossing of the positive edge of CK and negative edge of CK.

Output (read) data is referenced to the crossings of CK and CK (both directions of

crossing).

CKE

Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals

and device input buffers and output drivers. Taking CKE LOW provides Precharge

Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row

Active in any bank). CKE is synchronous for power down entry and exit, and for self

refresh entry. CKE is asynchronous for self refresh exit. After VREF has become

stable during the power on and initialization sequence, it must be maintained for

proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF

must be maintained to this input. CKE must be maintained HIGH throughout read and

write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during

power-down. Input buffers, excluding CKE, are disabled during self refresh.

Input

Chip Select: All commands are masked when CS is registered HIGH. CS provides for

external Rank selection on systems with multiple Ranks. CS is considered part of the

command code.

ODT

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal

to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, DM

signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT.

RAS

, CAS, WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being

entered.

DM (x8) or

UDM, LDM (x16)

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH coincident with that input data during a Write access. DM

is sampled on both edges of DQS. Although DM pins are input only, the DM loading

matches the DQ and DQS loading. For x8, the function of DM is enabled by EMRS

command to EMR(1) [A11].

BA0 - BA2

Input

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or

Precharge command is being applied. Bank address also determines if the mode

EMRS command cycle.

A0 - A13

Input

Address Inputs: Provide the row address for Active commands and the column

address and Auto Precharge bit for Read/Write commands to select one location

out of the memory array in the respective bank. A10 is sampled during a Precharge

command to determine whether the Precharge applies to one bank (A10 LOW) or all

banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0 -

BA2. The address inputs also provide the op-code during MRS or EMRS commands.

PIN DESCRIPTION TABLE

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