14

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

Symbol

Conditions

-25D/-25E

-3D

-37C

-5B

Units

DDR2-

800D/800E

DDR2-

667D

DDR2-

533C

DDR2-

400B

reads,

IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS

= tRASmax(IDD), tRP = tRP(IDD);

CKE is HIGH, CS is HIGH between valid commands;

345

275

230

190

mA

Address bus inputs are SWITCHING; Data pattern is same as

IDD4W

tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval;

230

185

175

170

mA

CKE is HIGH, CS is HIGH between valid commands; Other control

and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD6

Self refresh current;

CK and CK at 0 V; CKE

≤ 0.2 V;

Other control and address bus inputs are FLOATING;

3

3

3

3

mA

Data bus inputs are FLOATING

IDD7

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL

= tRCD(IDD) - 1 x tCK(IDD);

tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD),

tRCD = 1 x tCK(IDD);

CKE is HIGH, CS is HIGH between valid commands; Address bus

inputs are STABLE during DESELECTs;

Data pattern is same as IDD4R

370

350

340

265

mA

IDD Specifications & Test Conditions (continued)

Notes:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of

EMR(1) bits 10 and 11.

5. For DDR2-667/800 testing, tCK in the Conditions should be interpreted as tCK(avg)

6. Definitions for IDD

LOW = Vin ≤ VILAC(max)

HIGH = Vin ≥ VIHAC(min)

STABLE = inputs stable at a HIGH or LOW level

FLOATING = inputs at VREF = VDDQ/2

SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs

changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.

7. The -25E, -37C, and-5B device specifications are shown for reference only.