IS46DR16640C datasheet(22/49 Pages) ISSI

22 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.

6. All voltages are referenced to VSS.

7. These parameters guarantee device behavior, but they are not necessarily tested on each device They may be

guaranteed by device design or tester correlation.

8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply

voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

Specific Notes for Dedicated AC Parameters

1. User can choose which active power down exit timing to use via Mode Register Set [A12]. tXARD is expected to be

used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing.

2. AL = Additive Latency.

3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and

tRAS(min) have been satisfied.

4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.

5. Timings are specified with command/address input slew rate of 1.0 V/ns. See Specific Notes on derating for other

slew rate values.

6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns. See

Specific Notes on derating for other slew rate values.

tDS

tDH

tWPRE

tWPST

tDQSH

tDQSL

DQS

DMin

DQS/

tDH

DMin

DQS

VIL(ac)

VIH(ac)

VIL(ac)

VIH(ac)

VIL(dc)

VIH(dc)

VIL(dc)

VIH(dc)

tCH

tCL

CK/CK

DQS/DQS

DQS

tRPST

tRPRE

tDQSQmax

tQH

tDQSQmax

Data Input (Write) Timing

Data Output (Read) Timing

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