IS46DR16640C datasheet(43/49 Pages) ISSI

43 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

DESELECT

The DESELECT function (CS HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2

SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as

COMMAND INHIBIT.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS is LOW;

RAS

, CAS, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states.

Operations already in progress are not affected.

MODE REGISTER SET (MRS or EMRS)

The mode registers are loaded via bank address and address inputs. The bank address balls determine which mode

commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until

tMRD is met.

ACTIVATE

The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value

on the bank address inputs determines the bank, and the address inputs select the row. This row remains active (or

open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued

before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on the bank address inputs

determine the bank, and the address provided on address inputs A0–A9 selects the starting column location. The

value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being

accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open

for subsequent accesses.

DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to tRCD

(MIN) by delaying the actual registration of the READ/WRITE command to the internal device by AL clock cycles.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the bank select inputs

selects the bank, and the address provided on inputs A0–A9 selects the starting column location. The value on input

A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent

accesses.

DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to tRCD

(MIN) by delaying the actual registration of the READ/WRITE command to the internal device by AL clock cycles.

Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident

with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM

signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that

byte/column location.

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