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35

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

DDR2 SDRAM Mode Register Set (MRS)

Address

Field

Mode

Register

BA1

0

A12

Active power down exit time

BA0

0

0

Fast exit (use tXARD)

1

Slow exit(use tXARDS)

A11

A10

A9

A12

A13

0

PD

000

Reserved

001

2

A11

WR

010

3

011

4

A10

10

0

5

101

6

A9

110

Reserved

111

Reserved

A8

DLL

A8

DLL Reset

A7

Mode

A7

TM

0

No

0

Normal

1

Yes

1

Reserved

A6

CAS

Latency

A6

A5

A4

CAS Latency

A5

000

Reserved

001

Reserved

A4

010

Reserved

011

A3

BT

100

1

01

A2

Burst

Length

110

111

A1

A3

Burst Type

A2

A1

A0

BL

A0

0

Sequential

01

04

1

Interleave

01

18

Notes:

1. For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock

cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU

stands for round up). For DDR2-667/800, WR min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] =

RU{ tWR[ns] / tCK(avg)[ns] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP

to determine tDAL.

2. Speed bin determined. Refer to Key Timing Parameter table.

3. A13, only applicable for x8.