IS46DR16640C datasheet(27/49 Pages) ISSI

27 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to

the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and

tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due

to crosstalk ( tJIT(crosstalk)) into the clock traces.

12. tQH = tHP – tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL). tQHS

accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,

both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of

the output drivers.

13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output

drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

14. tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.

WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round

up to the next highest integer. tCK refers to the application clock period.

Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks.

tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of

clock frequency change during precharge power-down, a specific procedure is required as described in section 3.13.

16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn

on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently

per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH

if tCK = 5 ns. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH

counting the actual input clock edges.

17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when

the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For

DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT LOW if tCK = 5 ns.

For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge

counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.

18. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced

to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .

One method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) is by measuring the

signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is

consistent. tLZ(DQ) refers to tLZ of the DQ’s and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and (U/L/R)DQS each

treated as single-ended signal.

19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device

output is no longer driving (tRPST), or begins driving (tRPRE). One method to calculate these points when the device

is no longer driving (tRPST), or begins driving (tRPRE) is by measuring the signal at two different voltages. The actual

voltage measurement points are not critical as long as the calculation is consistent.

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