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FS23 Scheda tecnica(PDF) 132 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 132 Page - NXP Semiconductors |
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132 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22.16 M_VSUP_COM_MSK Bit 15 14 13 12 11 10 9 8 Write - - - - - - I2C_CRC_M I2C_REQ_M Read 0 0 0 0 0 0 I2C_CRC_M I2C_REQ_M Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write SPI_CRC_M SPI_CLK_M SPI_REQ_M - VSHS_OV_M VSHS_UV_M VSUP_OV_M VSUP_UV_M Read SPI_CRC_M SPI_CLK_M SPI_REQ_M 0 VSHS_OV_M VSHS_UV_M VSUP_OV_M VSUP_UV_M Reset 0 0 0 0 0 0 0 0 Table 105. M_VSUP_COM_MSK register bit allocation Bit Symbol Description Inhibit VSUP_UV Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 0 VSUP_UV_M POR Inhibit VSUP_OV Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 1 VSUP_OV_M POR Inhibit VSHS_UV Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 2 VSHS_UV_M POR Inhibit VSHS_OV Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 3 VSHS_OV_M POR Inhibit SPI request error Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 5 SPI_REQ_M POR Inhibit SPI clock error Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 6 SPI_CLK_M POR Inhibit SPI CRC error Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 7 SPI_CRC_M POR Inhibit I2C request error Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 8 I2C_REQ_M POR Table 106. M_VSUP_COM_MSK register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 132 / 230 |
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