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FS23 Scheda tecnica(PDF) 133 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 133 Page - NXP Semiconductors |
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133 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description Inhibit I2C CRC error Interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 9 I2C_CRC_M POR Table 106. M_VSUP_COM_MSK register bit description...continued 22.17 M_IOWU_CFG Bit 15 14 13 12 11 10 9 8 Write LVI5_WUCFG LVIO4_WUCFG LVIO3_WUCFG - HVIO2_DGLT HVIO1_DGLT WK2_DGLT WK1_DGLT Read LVI5_WUCFG LVIO4_WUCFG LVIO3_WUCFG 0 HVIO2_DGLT HVIO1_DGLT WK2_DGLT WK1_DGLT Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write HVIO2_WUCFG HVIO1_WUCFG WK2_WUCFG WK1_WUCFG Read HVIO2_WUCFG HVIO1_WUCFG WK2_WUCFG WK1_WUCFG Reset 0 0 0 0 0 1 0 1 Table 107. M_IOWU_CFG register bit allocation Bit Symbol Description Configure WAKE1 wake-up polarity 00 Input comparator disabled in LP modes only (no consumption) 01 High-level wake-up is configured 10 Low-level wake-up is configured 11 Cyclic sense wake-up is configured 0 to 1 WK1_WUCFG POR Configure WAKE2 wake-up polarity 00 Input comparator disabled in LP modes only (no consumption) 01 High-level wake-up is configured 10 Low-level wake-up is configured 11 Cyclic sense wake-up is configured 2 to 3 WK2_WUCFG POR Configure HVIO1 wake-up polarity 00 Input comparator disabled in LP modes only (no consumption) 01 High-level wake-up is configured 10 Low-level wake-up is configured 11 Cyclic sense wake-up is configured 4 to 5 HVIO1_WUCFG POR Configure HVIO2 wake-up polarity 00 Input comparator disabled in LP modes only (no consumption) 01 High-level wake-up is configured 10 Low-level wake-up is configured 11 Cyclic sense wake-up is configured 6 to 7 HVIO2_WUCFG POR Table 108. M_IOWU_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 133 / 230 |
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