L99H92 datasheet(46/77 Pages) STMICROELECTRONICS

46 / 77 page

Event

Status

flag/bit

Global

status

byte bit

Device actions

DIAGN pin behavior

FSINB activation

FSIN

Active switch-off of all external MOSFETs with

maximum available gate current (all gate drivers

forced in sink switch mode). The OUTE control bit

is reset.

Pulled low if DGFSINE

is set

Charge pump not ready

NRDY

The gate drivers are disabled. A passive resistive

connection between gate and source of each

MOSFET is present.

Pulled low if

DGNRDYE is set

Charge pump low

CPLOW

Active switch-off of external LS MOSFETs with

maximum available gate current (LS gate drivers

forced in sink switch mode). Active switch-off of

external HS MOSFETs with maximum available

gate current as long as VCP>VDH+3 V, otherwise

passive/resistive turn off.

Pulled low if

DGCPLOWE is set

Watchdog fault

WDGF

Active switch-off of all external MOSFETs with

maximum available gate current (all gate drivers

forced in sink switch mode).The OUTE control bit is

reset.

Pulled low if

DGWDGFE is set

Digital input/output

overvoltage

DIOOV

Active switch-off of all external MOSFETs with

maximum available gate current (all gate drivers

forced in sink switch mode).

Pulled low if

DGDIOOVE is set

VDS monitoring (Leg x,

HS or LS)

DSHSx

DSLSx

For DSMON_CONFIG control bit set to one and

INPMODE control bit set to zero: active switch-off

of all external MOSFETs with maximum available

gate current (all gate drivers forced in sink switch

mode). In all the other cases: active switch-off of

affected leg external MOSFETs with maximum

available gate current (affected leg gate drivers

forced in sink switch mode).

Pulled low if DGDSxE

is set

VS<VSPOR_ON

Followed by

VS>VSPOR_OFF

RSTB

In standby mode the charge pump is switched off

together with the gate drivers, so a passive

resistance between gate and source switches off

the external MOSFETs as well. Once back in active

mode, all the registers are reset to default values,

the charge pump is automatically enabled (no need

to clear the RSTB bit) and the gate drivers are

disabled leaving just a passive resistance between

gate and source of each MOSFET.

By default pulled low

once out of standby

mode and until the

global status byte

RSTB bit is cleared by

any valid SPI

communication frame

VDD<VDDPOR_ON

Followed by

VDD>VDDPOR_OFF

Enable pin pulled low

Followed by

Enable pin pulled high

SPI error (parity bit, write/

read to/from wrong

address, CLK count

error, SDI stuck at, CSN

timeout)

SPIE

The operation linked to the invalid SPI frame is not

run.

Pulled low if DGSPIEE

is set

L99H92

Operating modes

DS14069 - Rev 4

page 46/77

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