L99H92 datasheet(25/77 Pages) STMICROELECTRONICS

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The SPI Burst Read bit indicates whether the burst read mode is available or not. The Burst Read can be used to

perform a device internal memory dump to the SPI Master.

The start of the Burst Read is like a normal Read Operation. The difference is that after the SPI Data Length the

CSN is not pulled high and the CLK will be continuously clocked. When the normal CLK max count is reached

(SPI data length) the consecutive addressed data is latched into the shift register. This procedure is performed

every time the CLK payload length is reached.

In case the automatically incremented address is not used by the device, undefined data is shifted out. An

automatic address overflow is implemented when address 3FH is reached.

The SPI Burst Read is limited by the CSN low timeout.

SPI data length

The SPI Data Length value indicates the length of the CLK count monitor which is running for all accesses to the

Device Registers. Any communication frame with a CLK count not equal to the reported one will trigger an SPI

error and the corresponding command/operation will be ignored.

Table 14. SPI data length

Bit 6

Bit 5

Bit 4

Description

DL2

DL1

DL0

invalid

16-bit SPI

24-bit SPI

32-bit SPI

…

64-bit SPI

Data consistency check (parity/CRC)

Table 15. Data consistency check

Bit 1

Bit 0

Description

not used

Parity used

CRC used

Invalid

Watchdog identification registers

The <WD Type 1> and <WD Type 2> ROM registers are defined as follows:

Table 16. WD type ROM registers

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WD1

WD0

WT5

WT4

WT3

WT2

WT1

WT0

Watchdog timeout/long open window WT[5:0] * 5 ms

OW1

OW0

CW3

CW2

CW1

CW0

Open window OW[1:0] *5 ms

Closed window CW[3:0] * 5 ms

L99H92

ST SPI 4.1

DS14069 - Rev 4

page 25/77

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