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L99H92 Scheda tecnica(PDF) 60 Page - STMicroelectronics

Il numero della parte L99H92
Spiegazioni elettronici  Half-bridge pre-driver for automotive applications
PDF  77 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99H92 Scheda tecnica(HTML) 60 Page - STMicroelectronics

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Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit
Name
Description
15
DGVDHOVE
Diagnostic output VDHOV enable control bit. Setting this bit enables VDHOV status flag to be
mapped on diagnostic output pin (DIAGN).
14
DGVDHUVE
Diagnostic output VDHUV enable control bit. Setting this bit enables VDHUV status flag to be
mapped on diagnostic output pin (DIAGN).
13
DGVSOVWE
Diagnostic output VSOVW enable control bit. Setting this bit enables VSOVW status flag to be
mapped on diagnostic output pin (DIAGN).
12
DGVDDOVE
Diagnostic output VDDOV enable control bit. Setting this bit enables VDDOV status flag to be
mapped on diagnostic output pin (DIAGN).
11
DGTWE
Diagnostic output TW enable control bit. Setting this bit enables TW status flag to be mapped
on diagnostic output pin (DIAGN).
10
DGTSDE
Diagnostic output TSD enable control bit. Setting this bit enables TSD status flag to be mapped
on diagnostic output pin (DIAGN).
9
DGFSINE
Diagnostic output FSIN enable control bit. Setting this bit enables FSIN status bit to be mapped
on diagnostic output pin (DIAGN).
8
DGNRDYE
Diagnostic output NRDY enable control bit. Setting this bit enables NRDY status bit to be
mapped on diagnostic output pin (DIAGN).
Table 61. Diagnostic control register DIAGCR (0x09) LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R)
DGCPLOWE
DGWDGFE
DGDIOOVE
DGDS1E
DGSPIEE
DGDS2E
RES
P
Diagnostic
output
CPLOW
enable bit
Diagnostic
output WDGF
enable bit
Diagnostic
output DIOOV
enable bit
Diagnostic
output leg 1
drain-source
monitoring
enable bit
Diagnostic
output SPIE
enable bit
Diagnostic
output leg 2
drain-source
monitoring
enable bit
Reserved bit Parity bit
Bit
Name
Description
7
DGCPLOWE
Diagnostic output CPLOW enable control bit. Setting this bit enables CPLOW status flag/bit to
be mapped on diagnostic output pin (DIAGN).
6
DGWDGFE
Diagnostic output WDGF enable control bit. Setting this bit enables WDGF status flag to be
mapped on diagnostic output pin (DIAGN).
5
DGDIOOVE
Diagnostic output DIOOV enable control bit. Setting this bit enables DIOOV status flag to be
mapped on diagnostic output pin (DIAGN).
4
DGDS1E
Diagnostic output DS1 enable control bit. Setting this bit enables DSHS1 and DSLS1 status
flags to be mapped on diagnostic output pin (DIAGN).
3
DGSPIEE
Diagnostic output SPIE enable control bit. Setting this bit enables SPIE global status byte bit to
be mapped on diagnostic output pin (DIAGN).
2
DGDS2E
Diagnostic output DS2 enable control bit. Setting this bit enables DSHS2 and DSLS2 status
flags to be mapped on diagnostic output pin (DIAGN).
1
RES
Reserved
0
P
Parity bit
L99H92
Control registers
DS14069 - Rev 4
page 60/77



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