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L99H92 Scheda tecnica(PDF) 41 Page - STMicroelectronics |
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L99H92 Scheda tecnica(HTML) 41 Page - STMicroelectronics |
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41 / 77 page ![]() Item Symbol Parameter Test condition Min. Typ. Max. Unit 5.13.28 ten SDO tri H SDO enable time from CSN falling edge: 3-state to high level on SDO CL = 50 pF; Iload = +1 mA; pull- down load to VDD - 50 200 ns 5.13.29 tdis SDO H tri From CSN rising with DO at high level to 3-states measured at 0.3 VDD CL = 50 pF; Iload = -1 mA; pull-down load to GND - 50 100 ns 5.13.30 td SDO SDO delay time VSDO < 0.3 VDD; VSDO > 0.7 VDD; CL = 50 pF - 30 60 ns 1. Guaranteed by design. Table 39. CSN timing Item Symbol Parameter Test condition Min. Typ. Max. Unit 5.13.31 tCSN_HI, min Minimum CSN high time, active mode Transfer of SPI- command to input register 6 μs 5.13.32 tCSNfail CSN low timeout Tested by scan 20 35 50 ms Figure 20. SPI transfer timing diagram GADG120920221042SA The SPI can be driven by a microcontroller with its SPI peripheral running in the mode: CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. L99H92 SPI electrical characteristics DS14069 - Rev 4 page 41/77 |
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