L99H92 datasheet(21/77 Pages) STMICROELECTRONICS

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For write access the Payload represents the new data written to the addressed register. For Read & Clear

commands the Payload defines which bits of the addressed Status Register will be cleared. In case of a ‘1’ at the

corresponding bit position the status flag will be cleared.

For a Read Operation, the Payload is not used. For functional safety reasons it is recommended to set unused

Payload to ‘0’.

SDO frame

The data-out frame consists of 24 bits (GSB (8 bits) + Data Byte 2 (8 bits) + Data Byte 1 (8 bits)).

The first eight transmitted bits contain the device related status information and are latched into the shift register

at the time of the Communication Start. These 8 bits are transmitted at every SPI transaction.

The subsequent bytes contain the payload data and are latched into the shift register with the eighth positive CLK

edge.

This could lead to an inconsistency of data between the GSB and Payload due to different shift register load

times. Anyhow, no unwanted status register clear should appear, as status information should just be cleared with

a dedicated bit clear after.

Figure 16. SDO frame

GADG120920221019SA

Global Status Byte (GSB)

DATA Byte 2

DATA Byte 1

RSTB

GSBN

SPIE

PLE

MSB

LSB

time

DATA Byte 3

time

Global status byte (GSB)

The global status byte bits, from Bit16 to Bit19, represent a logical OR combination of status flags and status bits

located in the status register DSR1. Therefore, no direct Read & Clear command can be performed on these GSB

bits.

Table 6. Global status byte

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

GSBN

RSTB

SPIE

Global status bit not (GSBN)

The GSBN is a logically NOR combination of global status byte bits from bit 16 to bit 22. This bit can also be used

as Global Error Flag without starting a complete communication frame as it is directly present on SDO after

pulling CSN low.

GSBN = 1 (No error)

GSBN = 0 (Error)

•

ReSeT bit (RSTB)

The RSTB bit indicates that all the device registers have been reset to default. By default, it is set to one coming

out from standby mode. It is reset automatically after any valid SPI communication frame.

•

SPI error bit (SPIE)

The SPIE bit is a logical OR combination of all the errors related to a wrong SPI communication.

Besides, the CLK count, the CSN low timeout and the SDI stuck at errors, the parity error and the read/write

from/to wrong address are reported here as well.

The SPIE bit is automatically cleared by any valid SPI communication frame.

L99H92

ST SPI 4.1

DS14069 - Rev 4

page 21/77

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