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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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L99H92 Scheda tecnica(PDF) 53 Page - STMicroelectronics |
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L99H92 Scheda tecnica(HTML) 53 Page - STMicroelectronics |
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53 / 77 page  Table 47. Status register DSR2 (0x02) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) FSINLS2 RES RES RES O1DS RES O2DS P Fail-safe input not effect on LS2 bit Reserved bit Reserved bit Reserved bit Output 1 digital status bit Reserved bit Output 2 digital status bit Parity bit Bit Name Description 7 FSINLS2 Fail-safe input not effect on LS2 bit. This bit indicates whether the LS2 gate driver is configured in sink switch mode (FSINLS2=1) because of the FSINLL set to one or not (FSINLS2=0). In case of no faults the FSINLS2 bit should be automatically set once the FSINLL is set and automatically reset once the FSINLL is reset. It is a read only bit, so it cannot be cleared by SPI. 6 RES Reserved 5 RES Reserved 4 RES Reserved 3 O1DS Output 1 digital status bit. This bit provides the SH1 output logic level respect to the programmed threshold in any operating conditions, no matter what the OUTE value is. When OUTE=0, this bit reflects the not filtered output of the LS1 off-state diagnostic comparator having the programmed OLTHH threshold. When OUTE=1, this bit reflects the not filtered output of the LS1 DSMonitoring comparator having the programmed VSCdx threshold. 2 RES Reserved 1 O2DS Output 2 digital status bit. This bit provides the SH2 output logic level respect to the programmed threshold in any operating conditions, no matter what the OUTE value is. When OUTE=0, this bit reflects the not filtered output of the LS2 off-state diagnostic comparator having the programmed OLTHH threshold. When OUTE=1, this bit reflects the not filtered output of the LS2 DSMonitoring comparator having the programmed VSCdx threshold. 0 P Parity bit 6.4 Control registers Table 48. Control register DCR (0x03) MSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R/W)(1) 0 (R/W)(2) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) INPMODE OUTE AFWE FWS DIS1 DIS2 DSMON_CONFIG OLH1L2 Input mode selection bit Outputs enable bit Active free- wheeling enable bit Free- wheeling selection bit Disable leg1 bit Disable leg2 bit DSMonitoring configuration bit Open load in off-state bit Bit Name Description 15 INPMODE Input mode selection control bit: full-bridge mode (reset) or dual half-bridge mode (set). This bit can be modified only when OUTE is reset, otherwise its value is frozen and it cannot be changed. L99H92 Control registers DS14069 - Rev 4 page 53/77 |
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