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L99H92 Scheda tecnica(PDF) 23 Page - STMicroelectronics |
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L99H92 Scheda tecnica(HTML) 23 Page - STMicroelectronics |
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23 / 77 page ![]() RAM address Description Access 0DH Reserved None 0CH Reserved (RESVDI) R 0BH Reserved (RESVDO) R/W 0AH Contro register (WDGTRDIS) R/W ... ... 02H Status register (DSR2) R 01H Status register (DSR1) R/C 00H Reserved None Table 10. Address definition - ROM access ROM Address Description Access 3FH <Advanced op.> W 3EH <GSB options> R ... 20H <SPI CPHA test> R 16H <WD bit pos. 4> R 15H <WD bit pos. 3> R 14H <WD bit pos. 2> R 13H <WD bit pos. 1> R 12H <WD type 2> R 11H <WD type 1> R 10H <SPI mode> R … 0AH <Silicon ver.> R ... 05H <Device n.4> R 04H <Device n.3> R 03H <Device n.2> R 02H <Device n.1> R 01H <Device family> R 00H <Company code> R Information registers The device information registers can be read by using OpCode ‘11’. After shifting out the GSB the 8-bit wide payload will be transmitted. By reading device information registers a communication width which is minimum 16 bits plus a multiple by 8 can be used. After shifting out the GSB followed by the 8bit wide payload a series of ‘0’ is shifted out at the SDO. Table 11. L99H92 information registers map ROM Address Description Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FH <Advanced Op.> 3EH <GSB Options> R → 0 0 0 1 0 0 0 0 L99H92 ST SPI 4.1 DS14069 - Rev 4 page 23/77 |
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