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L99H92 Scheda tecnica(PDF) 40 Page - STMicroelectronics |
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L99H92 Scheda tecnica(HTML) 40 Page - STMicroelectronics |
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40 / 77 page ![]() Item Symbol Parameter Test condition Min. Typ. Max. Unit CSN, CLK, DI, DIR, PWM and EN 1. Value of input capacity is not measured in production test. Parameter is guaranteed by design. Table 36. DI, CLK and CSN timing Item Symbol Parameter Test condition Min. Typ. Max. Unit 5.13.11 tCLK Clock period Tested by scan 250 - ns 5.13.12 tCLKH Clock high time Tested by scan 100 - ns 5.13.13 tCLKL Clock low time Tested by scan 100 - ns 5.13.14 tset CSN CSN setup time, CSN low before rising edge of CLK Tested by scan 150 - ns 5.13.15 tset CLK CLK setup time, CLK high before rising edge of CSN Tested by scan 150 - ns 5.13.16 tset SDI SDI setup time Tested by scan 25 - ns 5.13.17 thold SDI SDI hold time Tested by scan 25 - ns 5.13.18 tr in Rise time of input signal SDI,CLK, CSN Tested by scan - 25 ns 5.13.19 tf in Fall time of input signal SDI, CLK, CSN Tested by scan - 25 ns Note: See Figure 21. Table 37. SDO Item Symbol Parameter Test condition Min. Typ. Max. Unit 5.13.20 VSDOL Output low level ID = +4 mA 0.5 V 5.13.21 VSDOH Output high level ID = -4 mA VDD – 0.5 V 5.13.22 ISDOLK Tristate leakage current VCSN= VDD; 0 V < VSDO< VDD -10 10 μA 5.13.23 CSDO Tristate input capacitance Guaranteed by design 10 15 pF Table 38. SDO timing Item Symbol Parameter Test condition Min. Typ. Max. Unit 5.13.24 tr SDO SDO rise time CL = 50 pF; Iload = -1 mA - 25(1) ns 5.13.25 tf SDO SDO fall time CL = 50 pF; Iload = +1 mA - 25(1) ns 5.13.26 ten DO tri L SDO enable time from CSN falling edge: 3-state to low level on SDO CL = 50 pF; Iload = +1mA; pull-up load to VDD - 50 100 ns 5.13.27 tdis SDO L tri SDO disable time from CSN rising edge: low level to 3-state on SDO CL = 50 pF; Iload = +1mA; pull-up load to VDD - 50 100 ns L99H92 SPI electrical characteristics DS14069 - Rev 4 page 40/77 |
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