L99H92 datasheet(18/77 Pages) STMICROELECTRONICS

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Serial peripheral interface (SPI)

A 24-bit SPI is used for bidirectional communication with the microcontroller.

The microcontroller SPI peripheral must run in the following configuration:

CPOL = 0 and CPHA = 0.

In this configuration the input data is sampled by the low to high transition of the serial clock CLK, and the output

data is changed by the high to low transition of the serial clock CLK.

Any fault condition can be detected without even providing any serial clock CLK by setting CSN low. In fact, if

CSN = 0, the serial data output SDO pin will reflect the global error flag (GSBN bit of the global status byte) of the

device.

•

Chip select not (CSN)

The CSN input pin is used to address the SPI communication with the device. When CSN is high, the output pin

(SDO) is in high impedance. When CSN is low, the output pin (SDO) driver is enabled and a serial communication

can start. The information transferred during CSN = 0 is called a communication frame.

If CSN = low for t > tCSNfail the SDO output will be switched into high impedance to allow SPI communications

with other SPI nodes.

•

Serial data in (SDI)

The SDI input pin is used to transfer data into the device. The data applied to the SDI will be sampled at the rising

edge of the serial CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the CSN signal

the content of the shift register will be transferred to Data Input Register. The writing to the selected Data Input

more or less than 24 clock pulses are counted within one frame the complete frame will be ignored. This safety

function is implemented to avoid an activation of the output stages by any wrong communication frame.

Note: Due to this safety functionality, daisy chaining is not possible. Instead, a parallel operation of the SPI bus by

controlling the CSN signal of the connected IC’s is recommended.

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Serial data out (SDO)

The SDO output driver is activated by a logical low level at the CSN input and will go from high impedance to low

or high level depending on the global error flag value (GSBN bit). The first falling edge of the CLK input after a

high to low transition of the CSN pin transfers the next global status byte bit out. Each subsequent falling edge of

the CLK shifts the following bits out.

•

Serial clock (CLK)

The CLK input pin is used to synchronize the input and output serial bit streams. The data input (SDI) is sampled

at the rising edge of the CLK and the data output (SDO) will change with the falling edge of the CLK. The SPI can

work with a CLK frequency up to 4 MHz (1/tCLK).

4.1

ST SPI 4.1

The ST-SPI is a standard used in ST automotive ASSP devices.

This chapter describes the SPI protocol standardization. It defines a common structure of the communication

frames and defines specific addresses for product and status information.

The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to

adapt it to the individual functionality of a particular product. In addition, fail-safe mechanisms are implemented to

protect the communication from external influences and wrong or unwanted usage.

The device serial peripheral interface is compliant to the ST SPI standard rev. 4.1.

L99H92

Serial peripheral interface (SPI)

DS14069 - Rev 4

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