H8SSLASH2214 datasheet(634/936 Pages) RENESAS

634 / 936 page

Section 15 ROM

Rev.4.00 Sep. 18, 2008 Page 574 of 872

REJ09B0189-0400

15.9.3

Erase Mode

Flash memory erasing should be performed block by block following the procedure shown in the

erase/erase-verify flowchart shown in figure 15.15.

For the wait times (t

sswe, tsesu, tse, tce, tcesu, tsev, tsevr, tcev, tcswe) after bits are set or cleared in flash memory

control register 1 (FLMCR1) and the maximum number of erase operations (N), see section 18.6,

Flash Memory Characteristics.

To perform data or program erasure, make a 1-bit setting for the flash memory area to be erased in

erase block register 1 or 2 (EBR1 or EBR2) at least t

sswe µs after setting the SWE1 bit to 1 in flash

memory control register 1 (FLMCR1). Next, set up the watchdog timer to prevent overerasing in

the event of program runaway, etc. Set a value greater than (t

sesu + tse + tce + tcesu) µs as the WDT

overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the

ESU1 bit in FLMCR1, and after the elapse of t

sesu µs or more, the operating mode is switched to

erase mode by setting the E1 bit in FLMCR1. The time during which the E1 bit is set is the flash

memory erase time. Ensure that the erase time does not exceed t

se ms.

Note:

With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is

not necessary before starting the erase procedure.

15.9.4

Erase-Verify Mode

In erase-verify mode, data is read after memory has been erased to check whether it has been

correctly erased.

In erase-verify mode, data is read after memory has been erased to check whether it has been

correctly erased.

After the elapse of the erase time, erase mode is exited (the E1 bit in FLMCR1 is cleared to 0, then

the ESU1 bit is cleared to 0 at least t

ce µs later), the watchdog timer is cleared after the elapse of

cesu µs or more, and the operating mode is switched to erase-verify mode by setting the EV1 bit in

FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to

the addresses to be read. The dummy write should be executed after the elapse of tsev µs or more.

When the flash memory is read in this state (verify data is read in 16-bit units), the data at the

latched address is read. Wait at least t

sevr µs after the dummy write before performing this read

operation. If the read data has been erased (all 1), execute a dummy write to the next address, and

perform an erase-verify. If the read data has not been erased, set erase mode again and repeat the

erase/erase-verify sequence as before. However, ensure that the erase/erase-verify sequence is not

repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait

for at least t

cev µs. If erasure has been completed on all the erase blocks, clear the SWE1 bit in

H8S/2214 Scheda tecnica(PDF) 634 Page - Renesas Technology Corp

H8S/2214 Scheda tecnica(HTML) 634 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL