H8SSLASH2214 datasheet(635/936 Pages) RENESAS

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Section 15 ROM

Rev.4.00 Sep. 18, 2008 Page 575 of 872

REJ09B0189-0400

FLMCR1. If there are any unerased blocks, make a 1-bit setting for the flash memory block to be

erased, and repeat the erase/erase-verify sequence as before.

End of erasing

Start

Set SWE1 bit in FLMCR1

Set ESU1 bit in FLMCR

Set E1 bit in FLMCR1

tSSWE : Wait 1 µs

tSESU : Wait 100 µs

n = 1

Set EBR1 (2)

Enable WDT

tSE : Wait 10 ms

tCE : Wait 10 µs

tCESU : Wait 10 µs

tSEV : Wait 20 µs

Set block start address to verify address

tSEVR : Wait 2 µs

Wait 4 µs: tCEV

Start erase

Clear E1 bit in FLMCR1

Clear ESU1 bit in FLMCR1

Set EV1 bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV1 bit in FLMCR1

Wait 4 µs: tCEV

Clear EV1 bit in FLMCR1

Wait 100 µs: tCSWE

Disable WDT

Halt erase

Verify data = all "1"?

Last address of block?

End of

erasing of all erase

blocks?

Erase failure

Wait 100 µs: tCSWE

Clear SWE1 bit in FLMCR1

≥ 100?

← n + 1

Increment

address

Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.

2. Verify data is read in 32-bit (longword) units.

3. Set only one bit in EBR1 (2). More than one bit cannot be set.

4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.

Erasing must be performed in

block units.

Figure 15.15 Erase/Erase-Verify Flowchart

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