H8SSLASH2224 datasheet(648/1071 Pages) RENESAS

648 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 562 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

3MPIE

R/W

Multiprocessor Interrupt Enable (enabled only

when the MP bit in SMR is 1 in asynchronous

mode)

Write 0 to this bit in Smart Card interface mode.

When receive data including MPB = 0 is received,

receive data transfer from RSR to RDR, receive

error detection, and setting of the RERF, FER, and

ORER flags in SSR, are not performed.

When receive data including MPB = 1 is received,

the MPB bit in SSR is set to 1, the MPIE bit is

cleared to 0 automatically, and generation of RXI

and ERI interrupts (when the TIE and RIE bits in

SCR are set to 1) and FER and ORER flag setting

are enabled.

TEIE

R/W

Transmit End Interrupt Enable

Write 0 to this bit in Smart Card interface mode.

TEI cancellation can be performed by reading 1

from the TDRE flag in SSR, then clearing it to 0

and clearing the TEND flag to 0, or clearing the

TEIE bit to 0.

CKE1

CKE0

R/W

Clock Enable 0 and 1

Enables or disables clock output from the SCK pin.

The clock output can be dynamically switched in

GSM mode. For details, refer to section 15.7.8,

Clock Output Control.

When the GM bit in SMR is 0:

00: Output disabled (SCK pin can be used as an

I/O port pin)

01: Clock output

×: Reserved

When the GM bit in SMR is 1:

00: Output fixed low

01: Clock output

10: Output fixed high

11: Clock output

Legend:

×: Don’t care

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