Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

H8S/2224 Scheda tecnica(PDF) 650 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 650 Page - Renesas Technology Corp

Back Button H8S/2224 Datasheet HTML 646Page - Renesas Technology Corp H8S/2224 Datasheet HTML 647Page - Renesas Technology Corp H8S/2224 Datasheet HTML 648Page - Renesas Technology Corp H8S/2224 Datasheet HTML 649Page - Renesas Technology Corp H8S/2224 Datasheet HTML 650Page - Renesas Technology Corp H8S/2224 Datasheet HTML 651Page - Renesas Technology Corp H8S/2224 Datasheet HTML 652Page - Renesas Technology Corp H8S/2224 Datasheet HTML 653Page - Renesas Technology Corp H8S/2224 Datasheet HTML 654Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 650 / 1071 page
background image
Section 15 Serial Communication Interface (SCI)
Rev. 5.00 Aug 08, 2006 page 564 of 982
REJ09B0054-0500
Bit
Bit Name
Initial
Value
R/W
Description
5
ORER
0
R/(W)*
1
Overrun Error
Indicates that an overrun error occurred during
reception, causing abnormal termination.
[Setting condition]
When the next serial reception is completed while
RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER flag
is set to 1. In clocked synchronous mode, serial
transmission cannot be continued either.
[Clearing condition]
When 0 is written to ORER after reading ORER =
1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is cleared to
0.
4FER
0
R/(W)*
1
Framing Error
Indicates that a framing error occurred during
reception in asynchronous mode, causing
abnormal termination.
[Setting condition]
When the stop bit is 0
In 2 stop bit mode, only the first stop bit is checked
for a value to 1; the second stop bit is not checked.
If a framing error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the FER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
[Clearing condition]
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is
checked.
The FER flag is not affected and retains its
previous state when the RE bit in SCR is cleared to
0.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com