H8SSLASH2224 datasheet(651/1071 Pages) RENESAS

651 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 565 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

PER

R/(W)*

Parity Error

Indicates that a parity error occurred during

reception using parity addition in asynchronous

mode, causing abnormal termination.

[Setting condition]

When a parity error is detected during reception

If a parity error occurs, the receive data is

transferred to RDR but the RDRF flag is not set.

Also, subsequent serial reception cannot be

continued while the PER flag is set to 1. In clocked

synchronous mode, serial transmission cannot be

continued, either.

[Clearing condition]

When 0 is written to PER after reading PER = 1

The PER flag is not affected and retains its previous

state when the RE bit in SCR is cleared to 0.

TEND

Transmit End

Indicates that transmission has been ended.

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit

of a 1-byte serial transmit character

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DMAC*

2 or the DTC*3 is activated by

a TXI interrupt request and transfer

transmission data to TDR

MPB

Multiprocessor Bit

MPB stores the multiprocessor bit in the receive

data. When the RE bit in SCR is cleared to 0 its

previous state is retained.

MPBT

R/W

Multiprocessor Bit Transfer

MPBT stores the multiprocessor bit to be added to

the transmit data.

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