H8SSLASH2224 datasheet(649/1071 Pages) RENESAS

649 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 563 of 982

REJ09B0054-0500

15.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be

written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit

functions of SSR differ between normal serial communication interface mode and Smart Card

interface mode.

• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)

Bit

Bit Name

Initial

Value

R/W

Description

TDRE

R/(W)*

Transmit Data Register Empty

Displays whether TDR contains transmit data.

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and

data can be written to TDR

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DMAC*

2 or the DTC*3 is activated by

a TXI interrupt request and writes data to TDR

RDRF

R/(W)*

Receive Data Register Full

Indicates that the received data is stored in RDR.

[Setting condition]

When serial reception ends normally and receive

data is transferred from RSR to RDR

[Clearing conditions]

• When 0 is written to RDRF after reading RDRF

= 1

• When the DMAC*

2 or the DTC*3 is activated by

an RXI interrupt and transferred data from RDR

The RDRF flag is not affected and retains their

previous values when the RE bit in SCR is cleared

to 0.

If reception of the next data is completed while the

RDRF flag is still set to 1, an overrun error will

occur and the receive data will be lost.

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