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7480 Scheda tecnica(PDF) 133 Page - Renesas Technology Corp |
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7480 Scheda tecnica(HTML) 133 Page - Renesas Technology Corp |
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133 / 337 page ![]() 7480 Group and 7481 Group User's Manual 1-116 1.14 Serial I/O HARDWARE (1) Block Diagram of Clock Synchronous Serial I/O Figure 1.14.8 shows the block diagram of a clock synchronous serial I/O. Figure 1.14.8 Block Diagram of Clock Synchronous Serial I/O Transmit interrupt source selection bit (TIC) Receive buffer full flag (RBF) Receive interrupt request (RI) Division ratio 1/(n + 1) RxD SCLK XIN TxD P16 P14 P17 P15 Address 00E016 Receive buffer register Receive shift register Transmit buffer register Transmit shift register Serial I/O status register Address 00E116 Serial I/O control register Clock control circuit Baud rate generator Falling edge detection F/F 1/4 1/4 Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Clock control circuit 1/4 Serial I/O synchronous clock selection bit (SCS) BRG count source selection bit (CSS) Transmit enable bit (TE) Receive enable bit (RE) Address 00E416 SRDY SRDY output enable bit (SRDY) Serial I/O enable bit (SIOE) Data bus Data bus Address 00E016 Address 00E216 |
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