R7FA2L1AB2DFN datasheet(30/110 Pages) RENESAS

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Table 2.10

Operating and standby current (1) (2 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

LDO mode

DCDC

mode*12

Unit

Test

Conditions

Typ*10 Max

Supply

current*1

Middle-

speed

mode*2

Normal

mode

All peripheral

clocks disabled,

CoreMark code

executing from

flash*5

ICLK = 24 MHz

ICC

2.80

—

1.65

—

ICLK = 4 MHz

0.90

—

0.55

—

All peripheral

clocks enabled,

code executing

from flash*5

ICLK = 24 MHz

—

10.0

—

8.8

Sleep

mode

All peripheral

clocks disabled*5

ICLK = 24 MHz

0.70

—

0.45

—

ICLK = 4 MHz

0.55

—

0.35

—

All peripheral

clocks enabled*5

ICLK = 24 MHz

3.50

—

2.10

—

ICLK = 4 MHz

0.95

—

0.60

—

Increase during BGO operation*6

2.00

—

1.65

—

Supply

current*1

Low-

speed

mode*3

Normal

mode

All peripheral

clocks disabled,

CoreMark code

executing from

flash*5

ICLK = 2 MHz

ICC

0.33

—

All peripheral

clocks enabled,

code executing

from flash*5

ICLK = 2 MHz

—

3.1

—

Sleep

mode

All peripheral

clocks disabled*5

ICLK = 2 MHz

0.13

—

All peripheral

clocks enabled*5

ICLK = 2 MHz

0.35

—

Subosc-

speed

mode*4

Normal

mode

All peripheral

clocks enabled,

code executing

from flash*5

ICLK = 32.768

kHz

ICC

—

540

—

µA

Sleep

mode

All peripheral

clocks disabled*5

ICLK = 32.768

kHz

2.00

—

All peripheral

clocks enabled*5

ICLK = 32.768

kHz

5.85

—

Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs

are in the off state.

In LDO mode, the supply current is total current flowing into VCC.

In DCDC mode, the supply current is total current flowing into VCC and VCC_DCDC.

Note 2. The clock source is HOCO.

Note 3. The clock source is MOCO.

Note 4. The clock source is the sub-clock oscillator.

Note 5. This does not include BGO and A/D operation.

Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.

Note 7. PCLKB and PCLKD are set to divided by 64.

Note 8. PCLKB and PCLKD are the same frequency as that of ICLK.

Note 9. PCLKB are set to be divided by 2 and PCLKD is the same frequency as that of ICLK.

Note 10. VCC = 3.3 V.

Note 11. The prefetch is operating.

Note 12. VCC = AVCC0 = VCC_DCDC = 2.4 to 5.5 V

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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