R7FA2L1AB2DFN datasheet(72/110 Pages) RENESAS

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Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.

Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.

Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.

Table 2.48

Power-on reset circuit and voltage detection circuit characteristics (2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Wait time after power-on

reset cancellation

LVD0: enable

tPOR

—

4.3

—

LVD0: disable

tPOR

—

3.7

—

Wait time after voltage

monitor 0, 1, 2 reset

cancellation

LVD0: enable*1

tLVD0,1,2

—

1.4

—

LVD0: disable*2

tLVD1,2

—

0.7

—

Power-on reset response delay time*3

tdet

—

500

µs

Figure 2.42, Figure 2.43

LVD0 response delay time*3

tdet

—

500

µs

Figure 2.44

LVD1 response delay time*3

tdet

—

350

µs

Figure 2.45

LVD2 response delay time*3

tdet

—

600

µs

Figure 2.46

Minimum VCC down time

tVOFF

500

—

µs

Figure 2.42, VCC = 1.0 V or

above

Power-on reset enable time

tW (POR)

—

Figure 2.43, VCC = below 1.0

LVD1 operation stabilization time (after LVD1 is

enabled)

Td (E-A)

—

300

µs

Figure 2.45

LVD2 operation stabilization time (after LVD2 is

enabled)

Td (E-A)

—

1200

µs

Figure 2.46

Hysteresis width (POR)

VPORH

—

Hysteresis width (LVD0, LVD1 and LVD2)

VLVH

—

LVD0 selected

—

110

—

Vdet1_0 to Vdet1_2 selected

—

Vdet1_3 to Vdet1_9 selected

—

Vdet1_A to Vdet1_B selected

—

Vdet1_C to Vdet1_F selected

—

LVD2 selected

Note 1. When OFS1.LVDAS = 0.

Note 2. When OFS1.LVDAS = 1.

Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,

Vdet1, and Vdet2 for the POR/LVD.

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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