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R7FA2L1AB2DFN Scheda tecnica(PDF) 51 Page - Renesas Technology Corp |
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R7FA2L1AB2DFN Scheda tecnica(HTML) 51 Page - Renesas Technology Corp |
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51 / 110 page ![]() 2.3.9 SPI Timing Table 2.32 SPI timing (1 of 3) Parameter Symbol Min Max Unit*1 Test conditions SPI RSPCK clock cycle Master 2.7 V ≤ VCC ≤ 5.5 V tSPcyc 62.5 — ns Figure 2.28 C = 30 pF 2.4 V ≤ VCC < 2.7 V 125 — 1.8 V ≤ VCC < 2.4 V 250 — 1.6 V ≤ VCC < 1.8 V 500 — Slave 2.7 V ≤ VCC ≤ 5.5 V 187.5 — 2.4 V ≤ VCC < 2.7 V 375 — 1.8 V ≤ VCC < 2.4 V 750 — 1.6 V ≤ VCC < 1.8 V 1500 — RSPCK clock high pulse width Master tSPCKWH (tSPcyc - tSPCKr - tSPCKf) / 2 - 3 — ns Slave 3 × tPcyc — RSPCK clock low pulse width Master tSPCKWL (tSPcyc - tSPCKr - tSPCKf) / 2 - 3 — ns Slave 3 × tPcyc — RSPCK clock rise and fall time Output 2.7 V ≤ VCC ≤ 5.5 V tSPCKr, tSPCKf — 10 ns 2.4 V ≤ VCC < 2.7 V — 15 1.8 V ≤ VCC ≤ 2.4 V — 20 1.6 V ≤ VCC < 1.8 V — 30 Input — 1 µs RA2L1 Datasheet 2. Electrical Characteristics R01DS0385EJ0100 Rev.1.00 Aug 06, 2020 Page 51 of 110 |
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