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R7FA2L1AB2DFN Scheda tecnica(PDF) 94 Page - Renesas Technology Corp |
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R7FA2L1AB2DFN Scheda tecnica(HTML) 94 Page - Renesas Technology Corp |
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94 / 110 page  Table 3.4 Register description (2 of 15) Peripheral name Dim Dim inc. Dim index Register name Description Address offset Size R/W Reset value Reset mask SRAM — — — ECC1STS ECC 1-Bit Error Status Register 0xC3 8 R/W 0x00 0xFF SRAM — — — ECCETST ECC Test Control Register 0xC4 8 R/W 0x00 0xFF SRAM — — — ECCPRCR ECC Protection Register 0xC4 8 R/W 0x00 0xFF SRAM — — — ECCPRCR2 ECC Protection Register 2 0xD0 8 R/W 0x00 0xFF SRAM — — — ECCOAD SRAM ECC Error Operation After Detection Register 0xD8 8 R/W 0x00 0xFF BUS — — — BUSMCNTSYS Master Bus Control Register SYS 0x1008 16 R/W 0x0000 0xFFFF BUS — — — BUSMCNTDMA Master Bus Control Register DMA 0x100C 16 R/W 0x0000 0xFFFF BUS — — — BUS3ERRADD Bus Error Address Register 3 0x1820 32 R 0x00000000 0x00000000 BUS — — — BUS3ERRSTAT BUS Error Status Register 3 0x1824 8 R 0x00 0xFE BUS — — — BUS4ERRADD Bus Error Address Register 4 0x1830 32 R 0x00000000 0x00000000 BUS — — — BUS4ERRSTAT BUS Error Status Register 4 0x1834 8 R 0x00 0xFE DTC — — — DTCCR DTC Control Register 0x00 8 R/W 0x08 0xFF DTC — — — DTCVBR DTC Vector Base Register 0x04 32 R/W 0x00000000 0xFFFFFFFF DTC — — — DTCST DTC Module Start Register 0x0C 8 R/W 0x00 0xFF DTC — — — DTCSTS DTC Status Register 0x0E 16 R 0x0000 0xFFFF ICU 8 0x1 0-7 IRQCR%s IRQ Control Register 0x000 8 R/W 0x00 0xFF ICU — — — NMICR NMI Pin Interrupt Control Register 0x100 8 R/W 0x00 0xFF ICU — — — NMIER Non-Maskable Interrupt Enable Register 0x120 16 R/W 0x0000 0xFFFF ICU — — — NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 R/W 0x0000 0xFFFF ICU — — — NMISR Non-Maskable Interrupt Status Register 0x140 16 R 0x0000 0xFFFF ICU — — — WUPEN Wake Up Interrupt Enable Register 0x1A0 32 R/W 0x00000000 0xFFFFFFFF ICU — — — IELEN ICU event Enable Register 0x1C0 8 R/W 0x00 0xFF ICU — — — SELSR0 SYS Event Link Setting Register 0x200 16 R/W 0x0000 0xFFFF ICU 32 0x4 0-31 IELSR%s ICU Event Link Setting Register %s 0x300 32 R/W 0x00000000 0xFFFFFFFF DBG — — — DBGSTR Debug Status Register 0x00 32 R 0x00000000 0xFFFFFFFF DBG — — — DBGSTOPCR Debug Stop Control Register 0x10 32 R/W 0x00000003 0xFFFFFFFF SYSC — — — SBYCR Standby Control Register 0x00C 16 R/W 0x0000 0xFFFF SYSC — — — MSTPCRA Module Stop Control Register A 0x01C 32 R/W 0xFFBFFFFF 0xFFFFFFFF SYSC — — — SCKDIVCR System Clock Division Control Register 0x020 32 R/W 0x04000404 0xFFFFFFFF SYSC — — — SCKSCR System Clock Source Control Register 0x026 8 R/W 0x01 0xFF SYSC — — — MEMWAIT Memory Wait Cycle Control Register for Code Flash 0x031 8 R/W 0x00 0xFF SYSC — — — MOSCCR Main Clock Oscillator Control Register 0x032 8 R/W 0x01 0xFF SYSC — — — HOCOCR High-Speed On-Chip Oscillator Control Register 0x036 8 R/W 0x00 0xFE SYSC — — — MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x038 8 R/W 0x00 0xFF SYSC — — — OSCSF Oscillation Stabilization Flag Register 0x03C 8 R 0x00 0xFE SYSC — — — CKOCR Clock Out Control Register 0x03E 8 R/W 0x00 0xFF SYSC — — — OSTDCR Oscillation Stop Detection Control Register 0x040 8 R/W 0x00 0xFF SYSC — — — OSTDSR Oscillation Stop Detection Status Register 0x041 8 R/W 0x00 0xFF SYSC — — — LPOPT Lower Power Operation Control Register 0x04C 8 R/W 0x00 0xFF SYSC — — — MOCOUTCR MOCO User Trimming Control Register 0x061 8 R/W 0x00 0xFF SYSC — — — HOCOUTCR HOCO User Trimming Control Register 0x062 8 R/W 0x00 0xFF SYSC — — — SNZCR Snooze Control Register 0x092 8 R/W 0x00 0xFF RA2L1 Datasheet Appendix 3. I/O Registers R01DS0385EJ0100 Rev.1.00 Aug 06, 2020 Page 94 of 110 |
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