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Table 2.33

IIC timing (2 of 2)

Conditions: VCC = AVCC0 = 2.7 to 5.5 V

Parameter

Symbol

Min*1

Max

Unit Test conditions

IIC (Fast mode)

SCL input cycle time

tSCL

6 (12) × tIICcyc + 600

—

Figure 2.35

SCL input high pulse width

tSCLH

3 (6) × tIICcyc + 300

—

SCL input low pulse width

tSCLL

3 (6) × tIICcyc + 300

—

SCL, SDA input rise time

tSr

—

300

SCL, SDA input fall time

tSf

—

300

SCL, SDA input spike pulse

removal time

tSP

1 (4) × tIICcyc

SDA input bus free time (When

wakeup function is disabled)

tBUF

3 (6) × tIICcyc + 300

—

SDA input bus free time (When

wakeup function is enabled)

tBUF

3 (6) × tIICcyc + 4 ×

tPcyc+ 300

—

START condition input hold time

(When wakeup function is

disabled)

tSTAH

tIICcyc + 300

—

START condition input hold time

(When wakeup function is enabled)

tSTAH

1 (5) × tIICcyc + tPcyc +

300

—

Repeated START condition input

setup time

tSTAS

300

—

STOP condition input setup time

tSTOS

300

—

Data input setup time

tSDAS

tIICcyc + 50

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

—

400

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle

Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

SDA0 and SDA1

SCL0 and SCL1

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Sr*1

Note:

n = 0, 1

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.35

I2C bus interface input/output timing

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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