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R7FA2L1AB2DFN Scheda tecnica(PDF) 99 Page - Renesas Technology Corp |
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R7FA2L1AB2DFN Scheda tecnica(HTML) 99 Page - Renesas Technology Corp |
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99 / 110 page  Table 3.4 Register description (7 of 15) Peripheral name Dim Dim inc. Dim index Register name Description Address offset Size R/W Reset value Reset mask CAN0 32 0x10 0-31 MB%s_ID Mailbox ID Register %s 0x200 32 R/W 0x00000000 0x00000001 CAN0 32 0x10 0-31 MB%s_DL Mailbox Data Length Register %s 0x204 16 R/W 0x0000 0x0000 CAN0 32 0x10 0-31 MB%s_D0 Mailbox Data Register %s 0x206 8 R/W 0x00 0x00 CAN0 32 0x10 0-31 MB%s_D1 Mailbox Data Register %s 0x207 8 R/W 0x00 0x00 CAN0 32 0x10 0-31 MB%s_D2 Mailbox Data Register %s 0x208 8 R/W 0x00 0x00 CAN0 32 0x10 0-31 MB%s_D3 Mailbox Data Register %s 0x209 8 R/W 0x00 0x00 CAN0 32 0x10 0-31 MB%s_D4 Mailbox Data Register %s 0x20A 8 R/W 0x00 0x00 CAN0 32 0x10 0-31 MB%s_D5 Mailbox Data Register %s 0x20B 8 R/W 0x00 0x00 CAN0 32 0x10 0-31 MB%s_D6 Mailbox Data Register %s 0x20C 8 R/W 0x00 0x00 CAN0 32 0x10 0-31 MB%s_D7 Mailbox Data Register %s 0x20D 8 R/W 0x00 0x00 CAN0 32 0x10 0-31 MB%s_TS Mailbox Time Stamp Register %s 0x20E 16 R/W 0x0000 0x0000 CAN0 8 0x04 — MKR[%s] Mask Register %s 0x400 32 R/W 0x00000000 0x00000000 CAN0 2 0x04 0-1 FIDCR%s FIFO Received ID Compare Register %s 0x420 32 R/W 0x00000000 0x00000000 CAN0 — — — MKIVLR Mask Invalid Register 0x428 32 R/W 0x00000000 0x00000000 CAN0 — — — MIER Mailbox Interrupt Enable Register 0x42C 32 R/W 0x00000000 0x00000000 CAN0 — — — MIER_FIFO Mailbox Interrupt Enable Register for FIFO Mailbox Mode 0x42C 32 R/W 0x00000000 0x00000000 CAN0 32 0x01 — MCTL_RX[%s] Message Control Register for Receive 0x820 8 R/W 0x00 0xFF CAN0 32 0x01 — MCTL_TX[%s] Message Control Register for Transmit 0x820 8 R/W 0x00 0xFF CAN0 — — — CTLR Control Register 0x840 16 R/W 0x0500 0xFFFF CAN0 — — — STR Status Register 0x842 16 R 0x0500 0xFFFF CAN0 — — — BCR Bit Configuration Register 0x844 32 R/W 0x00000000 0xFFFFFFFF CAN0 — — — RFCR Receive FIFO Control Register 0x848 8 R/W 0x80 0xFF CAN0 — — — RFPCR Receive FIFO Pointer Control Register 0x849 8 W 0x00 0x00 CAN0 — — — TFCR Transmit FIFO Control Register 0x84A 8 R/W 0x80 0xFF CAN0 — — — TFPCR Transmit FIFO Pointer Control Register 0x84B 8 W 0x00 0x00 CAN0 — — — EIER Error Interrupt Enable Register 0x84C 8 R/W 0x00 0xFF CAN0 — — — EIFR Error Interrupt Factor Judge Register 0x84D 8 R/W 0x00 0xFF CAN0 — — — RECR Receive Error Count Register 0x84E 8 R 0x00 0xFF CAN0 — — — TECR Transmit Error Count Register 0x84F 8 R 0x00 0xFF CAN0 — — — ECSR Error Code Store Register 0x850 8 R/W 0x00 0xFF CAN0 — — — CSSR Channel Search Support Register 0x851 8 R/W 0x00 0x00 CAN0 — — — MSSR Mailbox Search Status Register 0x852 8 R 0x80 0xFF CAN0 — — — MSMR Mailbox Search Mode Register 0x853 8 R/W 0x00 0xFF CAN0 — — — TSR Time Stamp Register 0x854 16 R 0x0000 0xFFFF CAN0 — — — AFSR Acceptance Filter Support Register 0x856 16 R/W 0x0000 0x0000 CAN0 — — — TCR Test Control Register 0x858 8 R/W 0x00 0xFF IIC0-1 — — — ICCR1 I2C Bus Control Register 1 0x00 8 R/W 0x1F 0xFF IIC0-1 — — — ICCR2 I2C Bus Control Register 2 0x01 8 R/W 0x00 0xFF IIC0-1 — — — ICMR1 I2C Bus Mode Register 1 0x02 8 R/W 0x08 0xFF IIC0-1 — — — ICMR2 I2C Bus Mode Register 2 0x03 8 R/W 0x06 0xFF IIC0-1 — — — ICMR3 I2C Bus Mode Register 3 0x04 8 R/W 0x00 0xFF IIC0-1 — — — ICFER I2C Bus Function Enable Register 0x05 8 R/W 0x72 0xFF IIC0-1 — — — ICSER I2C Bus Status Enable Register 0x06 8 R/W 0x09 0xFF IIC0-1 — — — ICIER I2C Bus Interrupt Enable Register 0x07 8 R/W 0x00 0xFF RA2L1 Datasheet Appendix 3. I/O Registers R01DS0385EJ0100 Rev.1.00 Aug 06, 2020 Page 99 of 110 |
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