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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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R7FA2L1AB2DFN Scheda tecnica(PDF) 37 Page - Renesas Technology Corp |
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R7FA2L1AB2DFN Scheda tecnica(HTML) 37 Page - Renesas Technology Corp |
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37 / 110 page  Independent watchdog timer reset Software reset Internal reset tRESWT3 tRESWIW, tRESWIR Figure 2.9 Reset input timing (2) 2.3.4 Wakeup Time Table 2.21 Timing of recovery from low power modes (1) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 High- speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz)*2 tSBYMC — 2 3 ms Figure 2.10 External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz)*3 tSBYEX — 2.4 3.1 µs System clock source is HOCO (HOCO clock is 32 MHz) tSBYHO — 4.9 6.2 µs System clock source is HOCO (HOCO clock is 48 MHz) tSBYHO — 4.8 6 µs System clock source is HOCO (HOCO clock is 64 MHz) tSBYHO — 4.9 6.2 µs System clock source is MOCO (8 MHz) tSBYMO — 4 5 µs Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00. RA2L1 Datasheet 2. Electrical Characteristics R01DS0385EJ0100 Rev.1.00 Aug 06, 2020 Page 37 of 110 |
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