R7FA2L1AB2DFN datasheet(91/110 Pages) RENESAS

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Table 3.1

Peripheral base address (2 of 2)

Name

Description

Base address

SCI9

Serial Communication Interface 9

0x4007_0120

SPI0

Serial Peripheral Interface 0

0x4007_2000

SPI1

Serial Peripheral Interface 1

0x4007_2100

CRC

CRC Calculator

0x4007_4000

GPT320

General PWM Timer 0 (32-bit)

0x4007_8000

GPT321

General PWM Timer 1 (32-bit)

0x4007_8100

GPT322

General PWM Timer 2 (32-bit)

0x4007_8200

GPT323

General PWM Timer 3 (32-bit)

0x4007_8300

GPT164

General PWM Timer 4 (16-bit)

0x4007_8400

GPT165

General PWM Timer 5 (16-bit)

0x4007_8500

GPT166

General PWM Timer 6 (16-bit)

0x4007_8600

GPT167

General PWM Timer 7 (16-bit)

0x4007_8700

GPT168

General PWM Timer 8 (16-bit)

0x4007_8800

GPT169

General PWM Timer 9 (16-bit)

0x4007_8900

GPT_OPS

Output Phase Switching Controller

0x4007_8FF0

KINT

Key Interrupt Function

0x4008_0000

CTSU

Capacitive Sensing Unit 2

0x4008_2000

AGT0

Low Power Asynchronous General Purpose Timer 0

0x4008_4000

AGT1

Low Power Asynchronous General Purpose Timer 1

0x4008_4100

ACMPLP

Low-Power Analog Comparator

0x4008_5E00

FLCN

Flash I/O Registers

0x407E_C000

Note:

Name = Peripheral name

Description = Peripheral functionality

Base address = Lowest reserved address or address used by the peripheral

3.2

Access Cycles

This section provides access cycle information for the I/O registers described in this manual.

The following information applies to Table 3.2:

● Registers are grouped by associated module.

● The number of access cycles indicates the number of cycles based on the specified reference clock.

● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations

cannot be guaranteed.

● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization

cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio

between ICLK and PCLK.

● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always

constant.

● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided

clock synchronization cycles.

Note:

This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the

external memory or bus access from other bus master such as DTC.

Table 3.2 shows the register access cycles for non-GPT modules.

RA2L1 Datasheet

Appendix 3. I/O Registers

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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