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R7FA2L1AB2DFN Scheda tecnica(PDF) 57 Page - Renesas Technology Corp

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Spiegazioni elettronici  Ultra low power 48 MHz Arm짰 Cortex-M23 core, up to 256-KB code flash memory
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2.3.10
IIC Timing
Table 2.33
IIC timing (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
Symbol
Min*1
Max
Unit Test conditions
IIC (standard mode,
SMBus)
SCL input cycle time
tSCL
6 (12) × tIICcyc + 1300
—
ns
Figure 2.35
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse
removal time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time (when
wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
—
ns
SDA input bus free time (when
wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 ×
tPcyc + 300
—
ns
START condition input hold time
(when wakeup function is disabled)
tSTAH
tIICcyc + 300
—
ns
START condition input hold time
(when wakeup function is enabled)
tSTAH
1 (5) × tIICcyc + tPcyc +
300
—
ns
Repeated START condition input
setup time
tSTAS
1000
—
ns
STOP condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
RA2L1 Datasheet
2. Electrical Characteristics
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
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