R7FA2L1AB2DFN datasheet(52/110 Pages) RENESAS

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Table 2.32

SPI timing (2 of 3)

Parameter

Symbol

Min

Max

Unit*1

Test

conditions

SPI Data input

setup time

Master

2.7 V ≤ VCC ≤ 5.5 V

tSU

—

Figure 2.29

to Figure

2.34

C = 30 pF

2.4 V ≤ VCC < 2.7 V 16 MHz < PCLKB ≤ 32

MHz

—

PCLKB ≤ 16 MHz

—

1.8 V ≤ VCC < 2.4 V 16 MHz < PCLKB ≤ 32

MHz

—

8 MHz < PCLKB ≤ 16

MHz

—

PCLKB ≤ 8 MHz

—

1.6 V ≤ VCC < 1.8 V

—

Slave

2.4 V ≤ VCC ≤ 5.5 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Data input

hold time

Master

(RSPCK is PCLKB/2)

tHF

—

Master

(RSPCK is not PCLKB/2)

tPcyc

—

Slave

—

SPI SSL setup

time

Master

1.8 V ≤ VCC ≤ 5.5 V

tLEAD

-30 + N ×

tSPcyc*2

—

1.6 V ≤ VCC < 1.8 V

-50 + N ×

tSPcyc*2

—

Slave

6 × tPcyc

—

SSL hold

time

Master

tLAG

-30 + N ×

tSPcyc*3

—

Slave

6 × tPcyc

—

Data output

delay time

Master

2.7 V ≤ VCC ≤ 5.5 V

tOD

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Slave

2.7 V ≤ VCC ≤ 5.5 V

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

110

Data output

hold time

Master

tOH

—

Slave

—

Successive

transmission

delay time

Master

tTD

tSPcyc + 2 ×

tPcyc

8 × tSPcyc +

2 × tPcyc

Slave

6 × tPcyc

—

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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