R7FA2L1AB2DFN datasheet(38/110 Pages) RENESAS

38 / 110 page

Table 2.22

Timing of recovery from low power modes (2)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery

time from

Software

Standby

mode*1

Middle-

speed

mode

Crystal

resonator

connected to

main clock

oscillator

System clock

source is main

clock oscillator (20

MHz)*2

tSBYMC

—

Figure 2.10

External clock

input to main

clock

oscillator

System clock

source is main

clock oscillator (20

MHz)*3

VCC = 1.8 V to 5.5

tSBYEX

—

2.4

3.1

µs

System clock

source is main

clock oscillator (20

MHz)*3

VCC = 1.6 V to 1.8

—

11.7

System clock

source is

HOCO*4

VCC = 1.8 V to 5.5

tSBYHO

—

5.2

6.5

µs

VCC = 1.6 V to 1.8

—

13.2

System clock

source is

MOCO (8

MHz)

VCC = 1.8 V to 5.5

tSBYMO

—

µs

VCC = 1.6 V to 1.8

—

7.2

Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is

determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.

Note 4. The system clock is 24 MHz.

Table 2.23

Timing of recovery from low power modes (3)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery

time from

Software

Standby

mode*1

Low-speed

mode

Crystal

resonator

connected to

main clock

oscillator

System clock

source is main

clock oscillator (2

MHz)*2

tSBYMC

—

Figure 2.10

External clock

input to main

clock

oscillator

System clock

source is main

clock oscillator (2

MHz)*3

tSBYEX

—

14.5

µs

System clock source is MOCO (2

MHz)

tSBYMO

—

µs

Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is

determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.

Table 2.24

Timing of recovery from low power modes (4)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery time

from Software

Standby mode*1

Subosc-speed mode

System clock source is

sub-clock oscillator

(32.768 kHz)

tSBYSC

—

0.85

Figure 2.10

System clock source is

LOCO (32.768 kHz)

tSBYLO

—

0.85

1.2

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

Page 38 of 110

R7FA2L1AB2DFN Scheda tecnica(PDF) 38 Page - Renesas Technology Corp

R7FA2L1AB2DFN Scheda tecnica(HTML) 38 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL