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R7FA2L1AB2DFN Scheda tecnica(PDF) 93 Page - Renesas Technology Corp |
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R7FA2L1AB2DFN Scheda tecnica(HTML) 93 Page - Renesas Technology Corp |
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93 / 110 page  Table 3.3 Access cycles for GPT modules (2 of 2) Frequency ratio between ICLK and PCLK Number of access cycles Cycle unit Read Write PCLKD > ICLK > PCLKB 2 to 3 1 to 2 PCLKB 3.3 Register Descriptions This section provides information associated with registers described in this manual. Table 3.4 shows a list of registers including address offsets, address sizes, access rights, and reset values. Table 3.4 Register description (1 of 15) Peripheral name Dim Dim inc. Dim index Register name Description Address offset Size R/W Reset value Reset mask MPU — — — MMPUCTLA Bus Master MPU Control Register 0x000 16 R/W 0x0000 0xFFFF MPU — — — MMPUPTA Group A Protection of Register 0x102 16 R/W 0x0000 0xFFFF MPU 4 0x010 0-3 MMPUACA%s Group A Region %s access control register 0x200 16 R/W 0x0000 0xFFFF MPU 4 0x010 0-3 MMPUSA%s Group A Region %s Start Address Register 0x204 32 R/W 0x00000000 0x00000003 MPU 4 0x010 0-3 MMPUEA%s Group A Region %s End Address Register 0x208 32 R/W 0x00000003 0x00000003 MPU — — — SMPUCTL Slave MPU Control Register 0xC00 16 R/W 0x0000 0xFFFF MPU — — — SMPUMBIU Access Control Register for Memory Bus 1 0xC10 16 R/W 0x0000 0xFFFF MPU — — — SMPUFBIU Access Control Register for Internal Peripheral Bus 9 0xC14 16 R/W 0x0000 0xFFFF MPU — — — SMPUSRAM0 Access Control Register for Memory Bus 4 0xC18 16 R/W 0x0000 0xFFFF MPU — — — SMPUP0BIU Access Control Register for Internal Peripheral Bus 1 0xC20 16 R/W 0x0000 0xFFFF MPU — — — SMPUP2BIU Access Control Register for Internal Peripheral Bus 3 0xC24 16 R/W 0x0000 0xFFFF MPU — — — SMPUP6BIU Access Control Register for Internal Peripheral Bus 7 0xC28 16 R/W 0x0000 0xFFFF MPU — — — MSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0xD00 16 R/W 0x0000 0xFFFF MPU — — — MSPMPUCTL Stack Pointer Monitor Access Control Register 0xD04 16 R/W 0x0000 0xFEFF MPU — — — MSPMPUPT Stack Pointer Monitor Protection Register 0xD06 16 R/W 0x0000 0xFFFF MPU — — — MSPMPUSA Main Stack Pointer (MSP) Monitor Start Address Register 0xD08 32 R/W 0x00000000 0x00000000 MPU — — — MSPMPUEA Main Stack Pointer (MSP) Monitor End Address Register 0xD0C 32 R/W 0x00000000 0x00000000 MPU — — — PSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0xD10 16 R/W 0x0000 0xFFFF MPU — — — PSPMPUCTL Stack Pointer Monitor Access Control Register 0xD14 16 R/W 0x0000 0xFEFF MPU — — — PSPMPUPT Stack Pointer Monitor Protection Register 0xD16 16 R/W 0x0000 0xFFFF MPU — — — PSPMPUSA Process Stack Pointer (PSP) Monitor Start Address Register 0xD18 32 R/W 0x00000000 0x00000000 MPU — — — PSPMPUEA Process Stack Pointer (PSP) Monitor End Address Register 0xD1C 32 R/W 0x00000000 0x00000000 SRAM — — — PARIOAD SRAM Parity Error Operation After Detection Register 0x00 8 R/W 0x00 0xFF SRAM — — — SRAMPRCR SRAM Protection Register 0x04 8 R/W 0x00 0xFF SRAM — — — ECCMODE ECC Operating Mode Control Register 0xC0 8 R/W 0x00 0xFF SRAM — — — ECC2STS ECC 2-Bit Error Status Register 0xC1 8 R/W 0x00 0xFF SRAM — — — ECC1STSEN ECC 1-Bit Error Information Update Enable Register 0xC2 8 R/W 0x00 0xFF RA2L1 Datasheet Appendix 3. I/O Registers R01DS0385EJ0100 Rev.1.00 Aug 06, 2020 Page 93 of 110 |
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