R7FA2L1AB2DFN datasheet(34/110 Pages) RENESAS

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Table 2.18

Operation frequency in Subosc-speed mode

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Typ

Max

Unit

Operation

frequency

System clock (ICLK)*1*3

1.6 to 5.5 V

27.8528

32.768

37.6832

kHz

Peripheral module clock (PCLKB) *3

1.6 to 5.5 V

—

37.6832

Peripheral module clock (PCLKD)*2 *3

1.6 to 5.5 V

—

37.6832

Note 1. Programming and erasing the flash memory is not possible.

Note 2. The ADC12 cannot be used.

Note 3. See section x, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.

2.3.2

Clock Timing

Table 2.19

Clock timing

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

EXTAL external clock input cycle time

tXcyc

—

Figure 2.3

EXTAL external clock input high pulse width

tXH

—

EXTAL external clock input low pulse width

tXL

—

EXTAL external clock rising time

tXr

—

EXTAL external clock falling time

tXf

—

EXTAL external clock input wait time*1

tEXWT

0.3

—

µs

—

EXTAL external clock input frequency

fEXTAL

—

MHz

1.8 ≤ VCC ≤ 5.5

—

1.6 ≤ VCC < 1.8

Main clock oscillator oscillation frequency

fMAIN

—

MHz

1.8 ≤ VCC ≤ 5.5

—

1.6 ≤ VCC < 1.8

LOCO clock oscillation frequency

fLOCO

27.8528

32.768

37.6832

kHz

—

LOCO clock oscillation stabilization time

tLOCO

—

100

µs

Figure 2.4

IWDT-dedicated clock oscillation frequency

fILOCO

12.75

17.25

kHz

—

MOCO clock oscillation frequency

fMOCO

6.8

9.2

MHz

—

MOCO clock oscillation stabilization time

tMOCO

—

µs

—

HOCO clock oscillation frequency

fHOCO24

23.76

24.24

MHz

Ta = -40 to 105°C

1.6 ≤ VCC ≤ 5.5

fHOCO32

31.68

32.32

Ta = -40 to 105°C

1.6 ≤ VCC ≤ 5.5

fHOCO48

47.52

48.48

Ta = -40 to 105°C

1.6 ≤ VCC ≤ 5.5

fHOCO64

63.36

64.64

Ta = -40 to 105°C

1.6 ≤ VCC ≤ 5.5

HOCO clock oscillation stabilization time*3 *4

tHOCO24

tHOCO32

tHOCO48

tHOCO64

—

1.9

—

µs

Figure 2.5

Sub-clock oscillator oscillation frequency

fSUB

—

32.768

—

kHz

—

Sub-clock oscillation stabilization time*2

tSUBOSC

—

0.5

—

Figure 2.6

Note 1. Time until the clock can be used after the Main Clock Oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the

external clock is stable.

Note 2. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the sub-clock oscillator

after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time value recommended by the oscillator

manufacturer.

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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