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FS23 Scheda tecnica(PDF) 134 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 134 Page - NXP Semiconductors |
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134 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description Configure WAKE1 deglitcher time 0 WAKE1 deglitcher = 15 us 1 WAKE1 deglitcher = 65 us 8 WK1_DGLT POR, Write Configure WAKE2 deglitcher time 0 WAKE2 deglitcher = 15 us 1 WAKE2 deglitcher = 65 us 9 WK2_DGLT POR, Write Configure HVIO1 deglitcher time 0 HVIO1 deglitcher = 15 us 1 HVIO1 deglitcher = 65 us 10 HVIO1_DGLT POR, Write Configure HVIO2 deglitcher time 0 HVIO2 deglitcher = 15 us 1 HVIO2 deglitcher = 65 us 11 HVIO2_DGLT POR, Write Configure LVIO3 wake-up polarity 0 High-level wake-up is configured 1 Low-level wake-up is configured 13 LVIO3_WUCFG POR Configure LVIO4 wake-up polarity 0 High-level wake-up is configured 1 Low-level wake-up is configured 14 LVIO4_WUCFG POR Configure LVI5 wake-up polarity 0 High-level wake-up is configured 1 Low-level wake-up is configured 15 LVI5_WUCFG POR Table 108. M_IOWU_CFG register bit description...continued 22.18 M_IOWU_EN Bit 15 14 13 12 11 10 9 8 Write - - LVI5_WUEN LVIO4_WUEN LVIO3_WUEN Read 0 0 LVI5_WUEN LVIO4_WUEN LVIO3_WUEN Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write HVIO2_WUEN HVIO1_WUEN WK2_WUEN WK1_WUEN Read HVIO2_WUEN HVIO1_WUEN WK2_WUEN WK1_WUEN Reset 1 1 1 1 1 1 1 1 Table 109. M_IOWU_EN register bit allocation FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 134 / 230 |
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