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FS23 Scheda tecnica(PDF) 136 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 136 Page - NXP Semiconductors |
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136 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22.19 M_IOWU_FLG Bit 15 14 13 12 11 10 9 8 Write[1] LVI5_WU_I LVIO4_WU_I LVIO3_WU_I - - - - - Read LVI5_WU_I LVIO4_WU_I LVIO3_WU_I 0 HVIO2_ CYS_RDY HVIO1_ CYS_RDY HVIO2_CYC_S HVIO1_CYC_S Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write[1] HVIO2_WU_I HVIO1_WU_I - - - - WK2_WU_I WK1_WU_I Read HVIO2_WU_I HVIO1_WU_I WK2_ CYS_RDY WK1_ CYS_RDY WK2_CYC_S WK1_CYC_S WK2_WU_I WK1_WU_I Reset 0 0 0 0 0 0 0 0 Table 111. M_IOWU_FLG register bit allocation [1] Write 1 in a flag to clear it. Bit Symbol Description Report WAKE1 wake-up event 0 No wake-up by WAKE1 (level) or WAKE1 pin state did not change between two trigger event (cyclic sense) 1 Wake up by WAKE1 occurred (level) or WAKE1 pin state changed between two trigger event (cyclic sense) 0 WK1_WU_I POR or fail-safe or clear on write (write '1) Report WAKE2 wake-up event 0 No wake-up by WAKE2 (level) or WAKE2 pin state did not change between two trigger event (cyclic sense) 1 Wake up by WAKE2 occurred (level) or WAKE2 pin state changed between two trigger event (cyclic sense) 1 WK2_WU_I POR or fail-safe or clear on write (write '1) Report WAKE1 state at trigger point 0 State at trigger point captured at 0 1 State at trigger point captured at 1 2 WK1_CYC_S POR, or each trigger point Report WAKE2 state at trigger point 0 State at trigger point captured at 0 1 State at trigger point captured at 1 3 WK2_CYC_S POR, or each trigger point Report WAKE1 readiness for cyclic sense 0 Cyclic sense not ready 1 Cyclic sense ready 4 WK1_CYS_RDY POR Report WAKE2 readiness for cyclic sense 0 Cyclic sense not ready 1 Cyclic sense ready 5 WK2_CYS_RDY POR Report HVIO1 wake-up event 0 No wake-up by HVIO1 (level) or HVIO1 pin state did not change between two trigger event (cyclic sense) 1 Wake up by HVIO1 occurred (level) or HVIO1 pin state changed between two trigger event (cyclic sense) 6 HVIO1_WU_I POR or fail-safe or clear on write (write '1) Table 112. M_IOWU_FLG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 136 / 230 |
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