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FS23 Scheda tecnica(PDF) 139 Page - NXP Semiconductors

Il numero della parte FS23
Spiegazioni elettronici  Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
PDF  230 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS23 Scheda tecnica(HTML) 139 Page - NXP Semiconductors

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NXP Semiconductors
FS23
Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
Bit
Symbol
Description
Report LIN wake-up event
0 No wake-up by LIN
1 Wake-up by LIN occurred
1
LIN_WU_I
POR or fail-safe or clear on write (write '1)
Report LDT wake-up event
0 No wake-up by LDT
1 Wake-up by LDT occurred
2
LDT_WU_I
POR or fail-safe or clear on write (write '1)
Report GO2NORMAL request from MCU wake-up event
0 No wake-up by MCU GO2NORMAL request
1 Wake-up by MCU GO2NORMAL request occurred
4
GO2NORMAL_WU
POR or fail-safe or clear on write (write '1)
Report interrupt time out wake-up event
0 No wake-up by interrupt time out
1 Wake-up by interrupt time out occurred
5
INT_TO_WU
POR or fail-safe or clear on write (write '1)
Report V1 LPON undervoltage wake-up event
0 No wake-up by V1 LPON undervoltage
1 Wake-up by V1 LPON undervoltage occurred
6
V1_UVLP_WU
POR or clear on write (write '1)
Report watchdog max error failure wake-up event
0 No wake-up by max error failure
1 Wake-up by watchdog max error failure occurred
7
WD_OFL_WU
POR or fail-safe or clear on write (write '1)
Report RSTB assertion wake-up event
0 No wake-up by to RSTB assertion
1 Wake-up by to RSTB assertion occurred
8
EXT_RSTB_WU
POR or fail-safe or clear on write (write '1)
Report a fail-safe event
0 No fail-safe event
1 Fail-safe event occurred (FSM went to Fail-safe state)
9
FS_EVT
POR or clear on write (write '1)
Table 116. M_WU1_FLG register bit description...continued
22.22 M_TIMER1_CFG
Bit
15
14
13
12
11
10
9
8
Write
-
-
-
-
-
-
-
TIMER1_DLY
Read
0
0
0
0
0
0
0
TIMER1_DLY
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write
TIMER1_DLY
TIMER1_ON
TIMER1_PER
Read
TIMER1_DLY
TIMER1_ON
TIMER1_PER
Reset
0
0
0
0
0
0
0
0
Table 117. M_TIMER1_CFG register bit allocation
FS23
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 16 October 2024
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